LPC55S69 : MPU tables for RTOS

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LPC55S69 : MPU tables for RTOS

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EugeneHiihtaja
Senior Contributor I

Hello !

It is not clear does MPU in this MCU is cover peripheral area memory range.

By fixed TZ settings I can enable access to SPI3 to be done with NS-user privileges.

But I have 5 tasks what running with user privileges and all of them can access SPI3 naturally.

It means RW for SPI3 peripheral need to be set as part of one task MPU configuration.

Does it possible or MPU cover only real memory address range ?

It is not clear for datasheet of this MCU type.

Regards,

Eugene

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EugeneHiihtaja
Senior Contributor I

Hi !

I think MPU covers all space until PPB :

"

However, by using the Memory Protection Unit (MPU), the “Memory
Type” of an address space (except for the last 0.5 GB of the 4G space) can be modified.

"

It means by TZ setting , SPI can have access with NS-Priv and in task context inserted with NS-user whentask is active.

Regards,

Eugene

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soledad
NXP Employee
NXP Employee

Hello Eugene,

Does it possible or MPU cover only real memory address range ?

 ANSWER. Yes, ONLY real memory  can be access, take in consideration that the memory range, it is generic from ARM TZ, but the Peripheral registers are not like any other memory to secured.

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EugeneHiihtaja
Senior Contributor I

Hi !

I have defined in TX setting access to SPI3 as NS-Priv and if 

from rtos task with user priviliges (NS-User) I would like to access it, I should add it to MPU settings.

In other case it generate memory fault.

It means MPU have some effect to peripheral area .

How you can explain this finding 

Regards,

Eugene

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Sabina_Bruce
NXP Employee
NXP Employee

Hello Eugene, 

It looks like the last question was answered in your other post.

Please let me know if you have other questions.

Best Regards,

Sabina

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