LPC55S69 : CPU retention to SRAMX_3

[EugeneHiihtaja]

Hi !

In UM mentioned that is possible to select SRAMX area for CPU retention :

"If CPU retention used in power-down mode, SRAMX_2 (0x1400 6000 to 0x1400 65FF) is
used (total 1.5 KB) by default in power API and this is user configurable within SRAMX_2 and SRAMX_3.

"

But it is not clear how-to configure in use SRAMX_3 area instead of SRAMX_2.

What power API should be used ?

Regards,

Eugene

[soledad]

Hi,

According with the MCUXpresso SDK API Reference Manual

#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 (1UL << 3)
enable SRAMX_3 retention when entering in Low power modes.

I hope this helps, have a nice day!

Regards

Soledad

[EugeneHiihtaja]

Hi soledad‌ !

I think this constant is just used LOWPOWER_SRAMRETCTRL_RETEN_RAMX3  for tell what kind of SRAM area should retain.

And it not the same.

How-to force CPU retention backup to this area ?

Regards,

Eugene

[soledad]

Hi,

Please check the SDK lpcxpresso55s69_power_manager_lpc example,

you will find the following function:

POWER_EnterDeepPowerDown(APP_EXCLUDE_FROM_DEEPPOWERDOWN,
                                                     LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 |                                                             LOWPOWER_SRAMRETCTRL_RETEN_RAMX3,
                                                     WAKEUP_RTC_LITE_ALARM_WAKEUP, 1);

For this function

/**
 * @brief   Configures and enters in POWERDOWN low power mode
 * @param   exclude_from_pd:
 * @param   sram_retention_ctrl:
 * @param   wakeup_interrupts:
 * @param   cpu_retention_ctrl:  0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are
 RESERVED.

 * @return  Nothing
 *
 *          !!! IMPORTANT NOTES :
 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
 *           1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
 *           2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
 *           3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl")
 *           4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)
 reset)
 */

Regards

Soledad

[EugeneHiihtaja]

Hi soledad‌ !

For my undestanding that parameters means what kind of SRAM areas should retain during PowerDown

POWER_EnterPowerDown(APP_EXCLUDE_FROM_POWERDOWN, 0x7FFF,
WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1, 1);

mask 0x7FFF means thats whole SRAM should be retain and we use this mask as well.

Of course SRAMx3 should be set to be retained if it used.

"3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl")"

But how-to redirect CPU retention dump to this area is not clear at all.

"cpu_retention_ctrl:  0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are"

Retention parameter enable retention but not specify if it SRAMX2 or 3.

Regards,

Eugene

[soledad]

Hi,

From the user manual, please check the sram_retention_ctrl parameter

Have a nice day!

Soledad

[EugeneHiihtaja]

Hi soledad‌ !

sram_retention define what instances of SRAM are retained.

But I would like to use other instance than default for save CPU retention data-

"If CPU retention used in power-down mode, SRAMX_2 (0x1400 6000 to 0x1400 65FF) is
used (total 1.5 KB) by default in power API and this is user configurable within SRAMX_2 and SRAMX_3.

"

But it is not clear how-to configure in use SRAMX_3 area instead of SRAMX_2.

Regards,

Eugene