LPC55S36, I3C IBI does not work for some dynamic addresses

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LPC55S36, I3C IBI does not work for some dynamic addresses

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bell_huang
Contributor III

I'm running I3C on LPC55S36-EVK and find out that I3C In-Band Interrupt (IBI) does not work for some dynamic addresses.

This issue can be reproduced in Building an I3C Sensor Network Using LPC553x/LPC55S3x example. I3C_BusMasterCreate automatically assigns dynamic addresses to master and devices. By default, it assigns 0x09 to ICM42688P. It is no problem to receive IBI interrupt. (Note: Any tap on the board may generate an IBI interrupt from ICM42688P).

0x09.png

However, if a device was assigned to 0x40 and when the device raise an IBI interrupt, I3C SDA will be pulled down forever. To reproduce in previous example, we can reserve dynamic address from 0x08~0x3E, then I3C_BusMasterCreate automatically assigns dynamic address 0x3F to master device, and 0x40 to ICM42688P. (As the attachment i3c_sensor_network.c)

 

// Dynamic address: 0x40
// Reserve address 0x08~0x3E, then master=0x3F, icm42688p=0x40
for (uint8_t i = 8U; i <= 0x3E; i++)
{
    I3C_BusSetAddrSlot(&demo_i3cBus, i, kI3C_Bus_AddrSlot_Reserved);
}

 

0x40_1.png

Moreover, if a device was assigned to 0x41 and when the device want to raise an IBI interrupt, we can see infinite interrupts.

 

// Dynamic address: 0x41
// Reserve address 0x08~0x3F, then master=0x40, icm42688p=0x41
for (uint8_t i = 8U; i <= 0x3F; i++)
{
    I3C_BusSetAddrSlot(&demo_i3cBus, i, kI3C_Bus_AddrSlot_Reserved);
}

 

0x41.png

From my tests, all dynamic addresses above 0x40 do not work correctly, while all below 0x3F work correctly. According to MIPI I3C® v1.1.1 (June 2021) , most dynamic addresses are available, except for a few reserved addresses.

I3C Target Address Restrictions.png

Here are some other tests for reference:

0x30: No problem

0x31: No problem

0x3F: No problem

0x50: I3C SDA is pulled down forever

0x51: Infinite interrupts.

bell_huang_1-1708047358666.png

bell_huang_2-1708047398421.png

bell_huang_0-1708047301655.png

bell_huang_3-1708047457312.png

bell_huang_4-1708047486316.png

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Pls refer to section 42.3.2.5 Assigning dynamic addresses to I3C devices in RM of LPC553x, the dynamic address of I3C target should be less than 0x40 for IBI support.

Hope it can help you

BR

XiangJun Rong

xiangjun_rong_0-1708695093049.png

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Pls refer to section 42.3.2.5 Assigning dynamic addresses to I3C devices in RM of LPC553x, the dynamic address of I3C target should be less than 0x40 for IBI support.

Hope it can help you

BR

XiangJun Rong

xiangjun_rong_0-1708695093049.png

 

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bell_huang
Contributor III

Hi @xiangjun_rong ,

Thanks for your information. Section 42.5.1 in LPC553x Reference Manual  explains the reason of optimization.

Use MIBIRULES[MSB0] to obtain faster START header times. If the controller application assigns all I3C dynamic addresses to be less than 40h (it does not have MSB set), MIBIRULES[MSB0] can be set. When the controller emits 7Eh (broadcast) and a target does not drive the first bit low, the rest of the header can be at push-pull speeds. This speed is two times faster or more, depending on optimizations.

Auto-emit 7Eh speeds up the frame when used with MIBIRULES[MSB0]. It allows the processor to sleep when the frame starts automatically (in response to a target).

Section 5.1.2.2.2 in MIPI I3C BasicSM v1.1.1 (July 2021) has more details for I3C Address Arbitration Optimization.

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