Hi NXP Experts,
We are using the LPC55S28 SPI in Non-DMA and Master mode, we want to know whether the SPI transmit/receive functions is busy in bit-shift currently. But failed to achieve such a status field.
At first, we guess the TXEMPTY field in FIFOSTAT might be helpful, but not exactly since the last piece of data bits might be being shifted upon TXEMPTY becoming 1.
Then we tried to use SSD(Slave select de-assert) and SSA (Slave select assert) lables in STAT register, since the user's manual docuemnet UM11126 says "This flag is set whenever any slave select transitions from de-asserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy". But, UNfortunately, find that, the labels were not changed to 1, either stable or transient, after a transmission issued even with the SOC received an expected value from the device! Especially considering user's manual says the 1 could be cleared only by software to set a 1 to it, we did not capture the the labels changed to 1 which means it did not change!. Is there any problem?
Meanwhile, our Application SHOULD use a software controllable GPIO to be the chip select signal other than the pre-defined SSELx signals. Can We use the SSD or SSA to determin the whether the peripheral is busy in bit serial shift?
To determin whether the the peripheral is busy in serial-bit shift, and using a software controllable GPIO to be nCS for special timing, are very common applications of SPI bus. Please Help Clarify or share sample codes if any.
Thanks in advance !
