When I configure the [LPC5536] to run its main clock on FRO 96MHz, then the system runs faster than that of the when we configure it to run on 150MHz(via PLL) ?
This above observation is concluded based on timestamps from the console logs (and its consistent).
The code being used for 96MHz
POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
CLOCK_SetupFROClocking(12000000U);
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
CLOCK_SetupFROClocking(96000000U);
POWER_SetVoltageForFreq(96000000U);
CLOCK_SetFLASHAccessCyclesForFreq(96000000U);
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
The code being used for 150Mhz via PLL0:
POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
CLOCK_SetupFROClocking(12000000U);
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
CLOCK_SetupExtClocking(16000000U); /* Enable XTALHF clock */
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */
POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
/*!< Set up PLL */
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
const pll_setup_t pll0Setup = {
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
.pllndec = SYSCON_PLL0NDEC_NDIV(8U),
.pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
.pllRate = 150000000U,
.flags = PLL_SETUPFLAG_WAITLOCK
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
