Pacing by DMA requests for serial interfaces such as USART, I2C and I2S is described below by DMATX and DMARX in the FIFOCFG register.
"Generate a DMA request for the transmit function if the FIFO is not full."
"Generate a DMA request for the receive function if the FIFO is not empty."
On the other hand, each of TXLVL and RXLVL in the FIFOTRIG register can define each FIFO level trigger point.
I have tested using the USART DMA example in the SDK and it seems that a DMA request is generated for each data send/receive, regardless of TXLVL and RXLVL.
I understand that TXLVL and RXLVL are ignored for pacing by DMA requests and that burst transfer by DMA request is not supported, is that correct?
I have contacted TIC support about this.
Hello, my name is Pavel, and I will be supporting your case, let me review your information, only for being sure could you tell me the example are you based on?
Thank you for your daily support.
I would appreciate it if you respond to my case in TIC instead of this case.
I saw you have 3 cases with some differences in the DMA, for quality of service I will be following your case in one of these.
Thank you for your reply.
In the example below in the SDK, even if RXLVL is a value other than 0 (config.rxWatermark ≠ kUSART_RxFifo1), one data is always transferred to the destination buffer each time it is received (key input). RXLVL seems to be ignored by DMA.
/* Initialize the USART. */
* config.baudRate_Bps = 115200U;
* config.parityMode = kUSART_ParityDisabled;
* config.stopBitCount = kUSART_OneStopBit;
* config.txFifoWatermark = 0;
* config.rxFifoWatermark = 1;
* config.enableTx = false;
* config.enableRx = false;
config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE;
config.enableTx = true;
config.enableRx = true;
config.rxWatermark = kUSART_RxFifo8;
USART_Init(DEMO_USART, &config, DEMO_USART_CLK_FREQ);