LPC546xx SPI Always Stalled

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LPC546xx SPI Always Stalled

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guitardenver
Contributor IV

I am using the SDK for the SPI0 with Flexcomm0 for the LPC54605 MCU.

I am using the SPI_MasterTransferBlocking function. It works fine, but the SPI0->STAT stalled bit is always set and the MSTIDLE flag is never set to one again. Also the SSA flag is stuck to one as well.

I need to poll for the transfer to be complete, not poll for the FIFO to be empty. 

My SPI Init routine:

pastedImage_1.png

Once you start a transfer the STAT register looks like this:
pastedImage_2.png

And you can keep sending data just fine, but the STALLED bit stays set even when using the SPI_MasterTransferBlocking.And MSTIDLE never is set again.

I don't need to receive anything, I even set the RXIGNORE flag in FIFOWR. But that did nothing.

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jeremyzhou
NXP Employee
NXP Employee

Hi Matt Lang

Thanks for your reply.
Q1) Does that mean a 1 needs to be written to the ENDTRANSFER by design and it's just not clear in the Reference Manual?
-- Yes.

Have a great day,
TIC

 

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jeremyzhou
NXP Employee
NXP Employee

Hi Matt Lang,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Whether you can tell me which exactly demo you run for testing, in further, had you done some modification about the demo?
As I'd like to replicate the phenomenon on my site for checking.

Have a great day,
TIC

 

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guitardenver
Contributor IV

Jeremyzhou,

I was wondering if you had a chance to replicate what I am seeing and if you had any thoughts on it.

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jeremyzhou
NXP Employee
NXP Employee

Hi Matt Lang

Thanks for your reply.

I've already replicated the phenomenon, I think it should add some notes in the RM to clarify or describe this phenomenon, I'll report it to RM team to further checking.

pastedImage_1.png

Have a great day,
TIC

 

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guitardenver
Contributor IV

jeremyzhou,

Does that mean a 1 needs to be written to the ENDTRANSFER by design and it's just not clear in the Reference Manual?

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1,017 Views
jeremyzhou
NXP Employee
NXP Employee

Hi Matt Lang

Thanks for your reply.
Q1) Does that mean a 1 needs to be written to the ENDTRANSFER by design and it's just not clear in the Reference Manual?
-- Yes.

Have a great day,
TIC

 

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guitardenver
Contributor IV

I see this with the lpcxpresso54608_driver_examples_spi_polling_b2b_transfer_master demo project with no edits.

After it calls SPI_MasterTransferBlocking(EXAMPLE_SPI_MASTER, &xfer), it is stalled and the MSTIDLE bit is never set even if you continue to step through the code.

I did this on MCUXpresso IDE this time running on the LPCXpresso654xx dev board.

pastedImage_1.png

In my other code, my solution was to write a 1 to the ENDTRANSFER bit in the STAT register when the last byte is send is complete. This will terminate the transfer once the current one is over and will get out of stalled and set the MSTIDLE bit. But the datasheet does not mention that this needs to be done, so i'm assuming I should not have to do this.

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