LPC546xx Flexcomm maximum clock frequency

[NoahPendleton_Markforged]

Hello-

The LPC546xx manual has this note about Flexcomm clock selection:

(Section 24.4 of UM10912 Rev 2.4)

Remark: The Flexcomm Interface function clock frequency should not be higher than
48 MHz.

We've experimented with selecting a 96MHz Audio PLL clock output for the Flexcomm interface; with a 16x oversample setting, this lets us use the maximum 6Mbaud speed for the USART (and seems to be working properly).

Is this configuration supported? Can a 96MHz clock be selected for the Flexcomm peripherals?

Thanks!

[dlaw2]

Thank you for looking into this. It would be really nice to have a definite reply from someone who knows the reason for the limitation, instead of "I think it can be ignored" followed by "we think it is correct". The flexcomm peripheral works fine with a 96 MHz clock from all of our testing.

[xiangjun_rong]

Hi,

Anyway, I have asked the AE team what the 48MHz limitation  means exactly,  I will update the thread after I get reply.

BR

XiangJun Rong

[xiangjun_rong · Accepted solution]

Hi, all,

This is AE team reply:

"We need to follow UM, the maximum limit clock is 48M, this is due to design limitation."

BR

Xiangjun Rong

[NoahPendleton_Markforged]

Hi Xiangjun-

Thanks for checking, much appreciated! We'll use 48MHz as the input clock to the Flexcomm.

Thanks!
Noah

[xiangjun_rong]

Hi, Noah,

I think it is a general guide line for the Flexcomm interface, as you use USART module, pls refer to the section 7.17.8.4 USART in data sheet of LPC546xx. which can be downloaded from

https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mc...

As it says that the bit rate can reach up to 6.25M in asynchronous mode, the USART driving clock will be 16*6.25M=100M.

Hope it can help you

BR

XiangJun Rong

[dlaw2]

Are you certain that the Remark about 48 MHz can be ignored? If it is incorrect, then why is it written in the user manual?

Please note that it is possible to obtain a USART speed of 6.25M with a flexcomm clock of 48 MHz or less by setting a lower value of the OSR register.

[xiangjun_rong]

Hi, Noah,

I agree with you that reducing the oversampling from 16 bits can reduce the required uart driving clock frequency.

baud rate = [FCLK / oversample rate] / BRG divide

The BRG is USART Baud Rate Generator register,is a clock divider.

I have consulted with AE engineer, we think that the Remark about 48 MHz clock limitation is correct, you should follow up the clock limitation.

Hope it can help you

BR

Xiangjun rong