I am having a great deal of trouble setting the multiply / divide registers for the System PLL clock, specifically the MDEC register, SYSPLLCTRL, SYSPLLMDEC, SYSPLLNDEC, and SYSPLLPDEC.
The function "BOARD_BootClockPLL180M" in the SDK sets the boot clock to 180MHz, and uses the interal 12MHz FRO as the input to the system PLL, and sets MDEC, NDEC, and PDEC, using hard-coded values: 8191, 770, and 98 respectively.
There is pseudo-code provided in the reference manual for calculating the MDEC register value, but when I try to calculate it, I get a different number than what is in the example in the SDK.
Looking for help because I would like to generate a 144MHz boot clock from the System PLL, but I cannot decipher this section of the reference manual. Would prefer NOT installing MCUXpresso or any software tools. Just looking for how these register values are actually calculated.
Thank you for your help,
Evan
--UPDATE--
I realize this is over a year later, but I just remembered this and wanted to leave it out there for anyone who may need it in the future! Messing around a bit, I found a way to encode the MDEC register value for any given multiplier M and made a handy function for doing so. Cheers!
uint32_t EncodeMDEC(uint16_t M)
{
uint32_t x, MDEC = 0;
/* Find MDec */
switch (M)
{
case 0:
MDEC = 0x1FFFF;
break;
case 1:
MDEC = 0x18003;
break;
case 2:
MDEC = 0x10003;
break;
default:
x = 0x04000UL;
//uint32_t m = 0xFFFFFFFFUL;
for (uint32_t i = 0x8000; i >= 3UL; i--)
{
x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
if(i == M)
{
MDEC = (x & 0x1FFFF);
}
}
break;
}
return MDEC;
}
