LPC54114 SPI FIFOWR - Halfword Access?

[dkd]

I'm trying to write to the SPI FIFOWR register setting the lower 16 bits only (data to be shifted out).  The UM claims that this register can be accessed for data writes only (not updating configuration) and that halfword writes to the lower 16 bits or word writes with the upper 16 bits all zeros will result in preservation of the original configuration.  I have tried both methods as well as 16 bit DMA transfers and the configuration appears to be lost in all cases.  I verified that the generated assembly is what I expect.  The SPI peripheral is configured for 16bit transfers.

Has anyone experienced this or been able to write data only to this register?

Thanks!

[lenniearaki]

#lpc54114 #spi #dma Was this ever resolved for NXP LPC54114 DMA using 14/16-bit SPI?  My application would also like to DMA 16-bit words *without* changing the SPI configuration.  I tried chaining 1 32-bit ctrl+data followed by N-1 16-bit data transfers but this does not work with the LPC54114.

Does anyone know if the NXP LPC5410x processor shares this same bug/limitation?  (I know it *does not* support the Flex I/O SPI/USART/I2C peripheral but does support DMA transfers and Master/Slave SPI transfers - plus it has 512KB of Flash instead of 256KB.

-Lennie

[jeremyzhou]

Hi Don Kebort,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Actually, I'm not very clear with your question, and I was wondering if you can clarify it, it would be better if you can share the demo code.
Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[dkd]

Sorry I wasn't clear.  I will try to strip my code down to something I can post here.  In the meantime, let me try to explain.

The FIFO write data register as described on page 384 of UM10914 Rev 2.0 states:

"FIFOWR provides the possibility of altering some SPI controls at the same time as
sending new data. For example, this can allow a series of SPI transactions involving
multiple slaves to be stored in a DMA buffer and sent automatically.These added fields
are described for bits 16 through 27 below.
Each FIFO entry holds data and associated control bits. Before data and control bits are
pushed into the FIFO, the control bit settings can be modified. Halfword writes to just the
control bits (offset 0xE22) doesn't push anything into the FIFO. A zero written to the upper
halfword will not modify the control settings. Non-zero writes to it will modify all the control
bits. Note that this is a write only register. Do not read-modify-write the register."

The part in bold is what I am struggling with.  In my application I only want to shift out new data without changing the configuration (upper 16 bits).  If I write to the lower 16 bits (data field) without writing the upper 16 bits (configuration), or with the upper 16 bits set to zero, the configuration is still overwritten.  This requires me to always write all 32 bits.  My options are to either double the size of my look-up table to also contain the configuration word, or to perform an intermediate DMA write, pulling my 16bit of data from the LUT, combining it in RAM with the configuration bits, and then moving the 32bit concatenated value to the SPI peripheral.  Option one requires too much memory, option two adds too much latency.

I hope this is a little more clear.  Thanks in advance for any help you can provide!

[jeremyzhou]

Hi Don Kebort,
Thanks for your reply.
The FIFOWR register seems like an organzation, you'd better not to divide it into two parts, write it via word unit.
Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[rstahl]

What does "The FIFOWR register seems like an organzation" mean?  Why doesn't the processor allow a half word write as describe in the documentation?

[jeremyzhou]

Hi Don Kebort,
Thanks for your reply.
To provide the fastest possible support, I'd highly recommend you to refer to the spi_dma_transfer in the SDK library for details.
https://www.nxp.com/support/developer-resources/software-development-tools/mcuxpresso-software-and-t...
Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------