A few questions:
Regards --- Roger
On Flash accelerator, there is a bit of information about this in User Manual -4.5.33 Flash Configuration register. The basic concept come from Flash being speed limited at around 3xMHz (depending on wafer process & design), semiconductor suppliers use different techniques to speed things up... namely : Buffers for fetching (Instruction vs Data ), Pre-fetching (for more than 1 buffer), Wait State insertion. There is a trade-off between power & speed. Note :this is NOT Cache or Tightly Coupled Memory (TCM)... this part (most LPC) has no Cache.
As for SRAM in LPC5410x, it is always zero wait state (up to 100MHz).
Hope this is clear.