Thanks for your quick reply. I can only think that my IOCON may be wrong.
1) Even though FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE=1 my code writes kADC_ClockSynchronousMode
#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE
adcConfigStruct.clockMode = kADC_ClockSynchronousMode; /* Using sync clock source. */
#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE */
2) The board's ADC channels used are ADC[3]..ADC[10] and I periodically read the temperature ADC[0] at a much much slower rate using SeqB.
3) IOCON We looked at the user manual pdf's Type A IOCON registers section and we wrote:
We tried with and without the filter without any difference.
Maybe we need to enable the OD flag but you wrote disabled, I think.
OD Controls open-drain mode. 0
0 Normal. Normal push-pull output
1 Open-drain. Simulated open-drain output (high drive disabled).
//-------------------------------------------------------------------------
// FUNC = 0 always for ADC
//-------------------------------------------------------------------------
const uint32_t adc_pin_config = ( IOCON_ANALOG_EN | IOCON_INPFILT_OFF);
//-------------------------------------------------------------------------
// Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u
//-------------------------------------------------------------------------
CLOCK_EnableClock(kCLOCK_Iocon);
IOCON_PinMuxSet(IOCON,ANA_IN1_PORT_NUM,ANA_IN1_PIN_NUM,adc_pin_config);
IOCON_PinMuxSet(IOCON,ANA_IN2_PORT_NUM,ANA_IN2_PIN_NUM,adc_pin_config);
IOCON_PinMuxSet(IOCON,ANA_IN3_PORT_NUM,ANA_IN3_PIN_NUM,adc_pin_config);
IOCON_PinMuxSet(IOCON,ANA_IN4_PORT_NUM,ANA_IN4_PIN_NUM,adc_pin_config);
IOCON_PinMuxSet(IOCON,ANA_IN5_PORT_NUM,ANA_IN5_PIN_NUM,adc_pin_config);
IOCON_PinMuxSet(IOCON,ANA_IN6_PORT_NUM,ANA_IN6_PIN_NUM,adc_pin_config);
IOCON_PinMuxSet(IOCON,ANA_IN7_PORT_NUM,ANA_IN7_PIN_NUM,adc_pin_config);
IOCON_PinMuxSet(IOCON,ANA_IN8_PORT_NUM,ANA_IN8_PIN_NUM,adc_pin_config);