LPC51U68 current consumption too high in Deep Sleep

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LPC51U68 current consumption too high in Deep Sleep

Contributor I

We are aiming to use the LPC51U68 for a product that will be battery powered and on 24/7, and in deep sleep when quiescent.

At the moment we are developing on the LPCXpresso51U68 development board and for these tests I have removed all external connection except the USB debug lead.

With both my own code and the example project "lpcxpresso51u68_power_manager_lpc" I am measuring a deep sleep current of around 800uA on JP6, whereas the chip datasheet gives a maximum of 17uA.

Is this a limitation of the board, or is there extra code needed to further reduce the consumption?

Any help would be appreciated. It is a bit of a show stopper if we can't get this down to near the datasheet figure.

Many Thanks


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Contributor I

I have the same issue, have followed the Examples notes, datasheet and this thread, can observe around 370uA in deep sleep. and 17uA in Power down state on our prototype. 

All peripherals are off, using internal 12mhz FRO.

All pins that can be are set to outputs and low.

Really need to get sub 50uA as we need PInt to wake up us up we cant use power down state.

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Contributor I


Apologies for the delay. I have been away from work, but I am now back on this project, but looking at other aspects. I will return to this soon.

As you suggest I am using deep sleep rather than shutdown to maintain memory, the state of output pins and to be able to use GINT and PINT for wakeup.

 I thought that all clocks were stopped in deep sleep anyway but I have it in the back of my mind you have to switch to FRO12 before sleeping.

On a previous project using an LPC11xx and LPCOpen we used a similar technique and achieved a board current of around 50uA, we are hoping for a similar figure here.


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Contributor I

Some further progress.

Holding USB D+ and D- to ground has saved 50uA.

Adding the following line saved 100uA


So now we are at 360uA. the datasheet sheet says 18uA (at 25C)

In summary

Minimal hardware system. During tests nothing connected to any PIO.

All PIO programmed as GPIO ,no pullup/down, set to output 0V.

All other pins connected as datasheet table 5

From AHBCLKCTRL0/1 all non needed clocks disabled.

Everything powered down except SRAM0 via 


I have read what I think are the relevant sections of datasheet, user guide and SDK API.

I must be missing something, but now out of ideas.

Thanks for any help


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NXP TechSupport
NXP TechSupport

Hi timjanes

Thank you for you for posting your code and summarizing what you had done at the moment. 

I believe this will be helpful  to other users.

Please provide me additional time to check for further recommendations. 

Best regards, Diego. 

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NXP TechSupport
NXP TechSupport

Hi Tim,

I apologize for the delay. 

You may have checked this information, but here are some tips. 

Regarding software, you could use the POWER_EnablePD() function (from Power API ) to  power down modules before enter an sleep mode or during normal RUN mode. You can check the effect of the function on Power configuration register (PDRUNCFG0)  . For example if the BOD is not needed , it could be disabled. I do not recommend to disable RAM areas with this function because you can affect application execution. 

As you know the deep power down is a good measure on how low you can reduce current consumption. But I assume you desire to use deep sleep because of the wake up options.   

If you want to reduce power consumption you can switch the FRO oscillator for another clock source. You can have a nice overview of system clocking on Config Tools ->Clock view. 

Regards, Diego. 

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Contributor I

Thank you for your reply.

I had not seen the readme. It has helped somewhat, but I am still a long way off, seeing a curent of 450uA.

I have been through the schematic and set all pins to GPIO without pullup/pulldown. Those that are being driven by other sources on the board I have set as inputs and the all others as outputs driven low.

Looking at AHBCLKCTRL0/1 just before calling  POWER_EnterDeepSleep only ROM, FLASH, FMC and PINT are running.

I am calling


which I believe is turning off everything except SRAM0.

I have now built a minimal LPC51U68 system, started a new  project, used configtools to set all PIO to output, no pullup/down and initial value of 0. The clock is the 12Mhz FRO. With nothing connected to any PIO I am still seeing a current around 450uA, so presumably something is still powered on or being clocked.

Below is my very simple code. I have not yet setup any means of wakeup in this test.



#include <stdio.h>
#include "board.h"
#include "peripherals.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "LPC51U68.h"
#include "fsl_debug_console.h"
#include "fsl_gpio.h"
/* TODO: insert other include files here. */

/* TODO: insert other definitions and declarations here. */

* @brief Application entry point.
int main(void) {

volatile uint32_t count = 0;

/* Init board hardware. */
/* Init FSL debug console. -- NOT Using Console */
// BOARD_InitDebugConsole();

while (1)
   count = 0;
   GPIO_PinWrite(GPIO, 1U, 10U, 1); //turn off GREEN LED
   GPIO_PinWrite(GPIO, 1U, 9U, 1); // Turn off BLUE LED
   while ( count < 10000000) // Delay approx 10 secs
   count = 0;

   GPIO_PinWrite(GPIO, 0U, 29U, 1); // Turn off RED LED

   SYSCON->BODCTRL &= ~0x4; // Disable BOD
   SYSCON->BODCTRL |= 0x40;
   CLOCK_DisableClock(kCLOCK_Gpio0); // Turn off unneeded clocks

   POWER_EnterDeepSleep(SYSCON_PDRUNCFG_PDEN_SRAM0_MASK); // Enter deep sleep just leaving SRAM0 powered

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NXP TechSupport
NXP TechSupport

Hi timjames

I'm glad to help!

Since I´m doing home office  , it is difficult for me help you with  testings on my side. However I hope this can help you by the moment.

You can implement additional code to reduce the power consumption. 

As you may already know, the  project readme,  provides advice for this.

Here you can see some recommendations.  

  • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
  • Configure GPIO pins as outputs using the GPIO DIR register.
  • Write 1 to the GPIO CLR register to drive the outputs LOW.
  • All peripherals disabled.

Table 8. Peripheral configuration in reduced power modes provides information related to the active peripherals in power down modes.

Is factible that  some path related to the MCU VDD   could sink additional current.  

Best regards,Diego. 

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