LPC43xx Max External Flash/SDRAM?

[lpcware]

Content originally posted in LPCWare by RandyM on Tue Apr 30 11:20:56 MST 2013

I'm interested in using the EMC controller for flash and SDRAM, though I'm confused on what the limits are.  What is the maximum memory addressable by the EMC?  When reading the <a href="http://www.nxp.com/documents/user_manual/UM10503.pdf">user manual</a>, I'm having a hard time connecting the dots.  Here's what is throwing me for a loop:

<table border="0">
<tbody>
<tr>
<td style="border: 1px solid #000000;"><strong>Memory</strong></td>
<td style="border: 1px solid #000000;"><strong>Chapter 3, Memory Mapping, fig 4</strong></td>
<td style="border: 1px solid #000000;"><strong>Chapter 21, EMC, section 21.3</strong></td>
</tr>
<tr>
<td style="border: 1px solid #000000;">Flash</td>
<td style="border: 1px solid #000000;">16MB for each CS, 64MB total</td>
<td style="border: 1px solid #000000;">Refers to to 512MB, 256MB, and 128MB parts, which all exceed the per CS and total MB stated in the mapping</td>
</tr>
<tr>
<td style="border: 1px solid #000000;">SDRAM</td>
<td style="border: 1px solid #000000;">128MB for DCYS0, 258MB for the other 3, 896MB total</td>
<td style="border: 1px solid #000000;">"... upt to 256MB of data,' far less that 896MB!</td>
</tr>
</tbody>
</table>

Am I misinterpretting the tables and text?  Does the text mix mega-bits (Mb) and mega-bytes (MB) with a singular acronym (MB)?  896MB of SDRAM seems very disproportionate to 64MB of flash.

[lpcware]

Content originally posted in LPCWare by RandyM on Thu May 02 06:05:28 MST 2013

Thanks for the re-clarification.  Re-reading your original reply should I'm not sure how I came to 256MB flash (at least I shouldn't have).  Thanks again.

[lpcware]

Content originally posted in LPCWare by wmues on Thu May 02 00:28:23 MST 2013

Because the maximum static Memory (Nor Flash) area is small compared to the dynamic Memory area, it is the best to use dynamic memory for data AND code, and use an EMMC chip or SD card for flash storage.

(For performance reasons, you may want to place the stack in internal RAM).

[lpcware]

Content originally posted in LPCWare by wellsk on Wed May 01 13:51:29 MST 2013

<em>&gt;So my limit would be 256MByte of flash using four 512 Mbit nor FLASH ICs (one for each CS#)</em>

Sorry, this would only be 64MB max with NOR FLASH - there are only 4 16MByte regions for static memory, so that's 64MBytes MAX if all selects and all address lines are used.

If you don't need all the NOR FLASH devices for Execute in Place code, you can get creative with a few GPIOs and 'expand' the address bus using bank swapping.

<em>&gt;&gt;Refers to to 512MB, 256MB, and 128MB parts, which all exceed the per CS and total MB stated in the mapping</em>

<em><em>&gt;</em>This comment refers to MBits for DRAM based devices, which would be a 64MByte sized part for 512MB (max).</em>

These comments actually refer to DRAM and the DYCS signals, not static memory and the CS signals.<em>
</em>

[lpcware]

Content originally posted in LPCWare by RandyM on Wed May 01 08:06:28 MST 2013

So my limit would be 256MByte of flash using four 512 Mbit nor FLASH ICs (one for each CS#), and 256MByte of SDRAM using four 512 Mbit nor SDRAM ICs (one for each DCYS#).  Thanks!

[lpcware]

Content originally posted in LPCWare by wellsk on Tue Apr 30 15:37:00 MST 2013

Hi,

The memory mapping refers to addressable space assigned for that region, while the EMC info refers to the limitations for the EMC.

For the static memmory regions, you have 4x 16MB regions that can address 64MB max (using all 4 CS and all 24 address lines).

&gt;<em>Refers to to 512MB, 256MB, and 128MB parts, which all exceed the per CS and total MB stated in the mapping</em>

This comment refers to MBits for DRAM based devices, which would be a 64MByte sized part for 512MB (max).

&gt;<em>128MB for DCYS0, 258MB for the other 3, 896MB total</em>

This is also the size of the memory mapped region for DRAM. However, the maximum DRAM parts you could put on each DYCS line is 64MBytes (512MBit), so the maximum memory size for DRAM with all 4 DYCS signals being used is 256MByte. Accessing beyond the 64MByte range on a DRAM device will probably wrap the access back to the start of the device.<em></em>

<em>
</em>