LPC43xx I2S synchronisation question

[jonathansmith]

Hi,

I am using the I2S interface on a LPC4333. I have this set up and it is running fine. The next step is to re-synchronise (or deskew) the sampling when an external pulse occurs, which will be every 10s approx. What I want to achieve is the rising edge of I2S0_TX_MWS to be delayed. Since I am driving a slave ADC I think I should also be stopping the SCLK for the delay duration.

I am planning on using TIMER3 to count the number of PCLKs between my sync pulse and I2S0_TX_MWS, which will allow me to work out what delay is needed on the I2S interface to sync them up.

I am not sure how to delay the I2S interface. Should I stop and restart the interface? Should I also empty the buffer?  Should I mute? Will any of these guarantee that the I2S0_TX_MWS will be synced?

Any recommendations would be appreciated,

Jonathan

[jeremyzhou]

Hi Jonathan Smith,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
According to your statement, the MCU works as a master and your goal is the master will terminate sending data, in another word, SCLK and TX_WS pins will become inactive, isn't right?
However, I'm not clear with the mean of "re-synchronize ", I was wondering if you can explain it, as I'd like to get the more information to answer your question.
Have a great day,
TIC

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[jonathansmith]

Thanks for your response. After some testing and a little more development I have come up with a solution that half does what I want. I think it is acceptable for SCLK to keep running, it is TX_WS I am interested in manipulating.

What I am trying to achieve is (in the following order):

1) TX_WS and SCLK operating as normal. TX_WS at 10KHz and SCLK at 640KHz.

2) An asynchronous external event occurs which calls for the following to happen:

        a) TIMER2 is started

        b) TX_WS stops after it’s current cycle

        c) TX_WS is then restarted once TIMER2 matches a certain value

The purpose of this is to have TX_WS rising edge synchronised with the external event, even though it starts one to two cycles afterwards, ie exactly 0.1ms or 0.2ms after the external event. Our client expects the samples from the ADC to be done in this way.

I have been able to achieve this in part, by setting the reset bit in the I2S DAO register and starting TIMER2. Once TIMER2 matches the count value it triggers an interrupt which unsets the reset bit in the I2S DAO register and starts TX_WS up again.

It is part 2a that I am now struggling with. As soon as I set the reset bit in DAO the TX_WS signal goes low so I lose that sample. Is there a way to have TX_WS complete it’s current cycle?

I hope that is a little clearer.

[jeremyzhou]

Hi Jonathan Smith,
Thanks for your reply.
1) Is there a way to have TX_WS complete it’s current cycle?
-- Maybe you can add another restrict: enable an interrupt of set the FIFO level, and in this interrupt function, set the reset bit in DAO register when TIMER2 match event happens. It can assure not break the data transferring process and MCU can continue to transfer the rest of data after a restart.
Have a great day,
TIC

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