LPC43xx DMA with SSP

[JohnDeMar]

I am using an LPCLink2 as a target board. I have successfully set up two DMA channels for Tx and Rx with the SSP peripheral configured for SPI. I can run this as a one shot and the data is sent and returned (to/from an ADC chip). I began with the lpcopen_3_02_lpcxpresso_link2_4370.zip example project periph_ssp. I am using MCUXPresso.

When I use a Pin Interrupt to respond to the ADC ready line to start the transfer, I cannot get the DMA to respond quickly. The interrupt is happening at 60KHz when I simply toggling a pin. But it is very asynchonous and <8KHz when I try to start a short DMA transfer (less than the 60KHz period).

Is there an example somewhat related to what I am trying to do?  I'm assuming there must be a fast way to start/stop the DMA after configuring it once at power up. 

  -John DeMar

[JohnDeMar]

Thank you for the reply. I am already running the SSP bitrate clock at 20MHz. A single burst of ADC data works successfully and takes only 1.6.us. That is about 1/10th the period between the 60KHz "data ready" pin interrupt.

I have moved all of the code from SPIFI to internal RAM to make sure it is running without wait states. It doesn't seem to help much.

The problem is the delay from starting a DMA transfer to the actual transfer completion. It is missing many of the 60KHz interrupts before it will allow it to repeat.

I am looking through many other DMA examples on the LPX43xx and reading the DMA documentation in more detail. I will try to simplify the source code and post it here.

 -John

[Fan_xy]

Hi Jone,

I'm also working on the SSP with DMA, could you please share to me about how to measure the frequency of DMA

start,  and the time between trigger DMA and DMA start transfer .

Thank you very much.

Fan

[JohnDeMar]

Fan,

   I am using a GPIO pin to measure the DMA response. I set the output high when the pin interrupt happens at the ADC data ready. I set the output low in response to the DMA complete interrupt.

The SPI DATA OUT should begin immediately at the first 60KHz interrupt. The DMA IRQ should happen immediately after the SPI data is complete. The short burst of data is well within the 60KHz sample period. I cannot account for the 170us lag before the SPI DMA begins. Nor can I determine why it is taking 275us to after data is complete until the DMA IRQ happens.

  -John

[Alice_Yang]

Hello John,

After ADC data ready, SSP start transfer data from ADC chip to lpc4370 DATA register,

then DMA transfer data from SSP DATA register to a buffer you define.

DMA not start immediately after ADC data ready.

You can also have a look at the demo code about DMA configuration :

Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[Alice_Yang]

Hello John DeMar,

I'm afraid that if I understand your meaning correctly,

About "Pin Interrupt to respond to the ADC ready line to start the transfer, The interrupt is happening at 60KHz when I simply toggling a pin" - > Once the ADC data ready, there is a pin interrupt , the frequency is 60MHZ. While the DMA trigger frequency <8MHZ, right ?

If yes, you need increase the SSP clock rate ,  please check it  on your side . On the demo code " periph_ssp " ,   the bit rate is 100K.

Hope it helps,

Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------