LPC43XX DMA Control reg TRANSFERSIZE in NONE DMA flow control

[robberpen]

My case is ADCHS with DMA burst transfer.

1. ADCHS
2. DMA Flow control is peripheral  (0x6)
3. DMA Scatter/gather.
4. DMA Burst mode, in automatically transfer.

Questions

1. In case of Flow-Control is peripheral, DMA Control reg b[0:11] TRANSFERSIZE (see figure) set 0 is correct ?
2. How many size will be transfer a “DMA burst request” signal occur.
   Due to I only allocated 256 bytes for destination memory buffer.
   But the DMA keep transfers ata exceed > 256 bytes, and seems never switch to another target buffer I prepared on LLI(Link List Items) automatically.
   In other word, What is the condition leading DMA update (read) LLI to LLI.next

Thanks

[Harry_Zhang]

Hi @robberpen 

1. Setting TRANSFERSIZE to 0:
• Since the flow control is being managed by the peripheral (in this case, ADCHS), the TRANSFERSIZE field is not used to limit the number of transfers (as indicated by the red-highlighted text in your image). Instead, the peripheral controls the number of transfers in each burst, so setting the TRANSFERSIZE to 0 is valid when the peripheral is the flow controller.
2. DMA Burst Request and Transfer Size:
• The DMA burst request signal initiates the transfer. Typically, the burst size for each transfer is set in the burst size configuration of the DMA or ADCHS peripheral. If the burst transfer size exceeds 256 bytes (your allocated buffer size), you will run into issues, which might explain why your DMA is exceeding the 256-byte buffer. You’ll need to review your DMA burst size configuration in the ADCHS peripheral or the DMA settings to match it to your allocated buffer size.
3. DMA and Linked List Item (LLI) Switching:
• In scatter/gather mode, the DMA switches to the next LLI (Linked List Item) once the current transfer completes. If the DMA is not switching to the next LLI, it could indicate that the DMA doesn’t detect that the current buffer is full or the transfer size isn’t being processed correctly.

BR

Hang

[robberpen]

@Harry_Zhang 

Thanks your clarify

Based your 3rd reply

In scatter/gather mode, the DMA switches to the next LLI (Linked List Item) once the current transfer completes

What is the exactly defination of "transfer completes" for peripheral as flow-control(HSADC) ?

In this case I set DMA control register b[14:12] = burst (0x0 << 12) . that is means  DMA burst "transfer completed" in burst on 4 bytes  = (1(SBSIZE) x  4(SWIDTH))? then DMA will lookup next LLI or raise DMA ISR for furture set/confiig? see below another post for sample code.

But as my tested, The behavior is not like as what I expect. it never raise any DMA interrupt nor stop transfer untill SRAM been full-up.

https://community.nxp.com/t5/LPC-Microcontrollers/LPC4300-DMA-scatter-gatter-with-LLI/m-p/1953641#M5...

[Harry_Zhang]

Hi @robberpen 

I will reply in the link you mentioned.

BR

Hang