LPC4370 HSADC issue: Power supply noise coupling

[IrvinSirotia_]

Hello, 

I'm trying to use LPC4370FET256 (BGA) device with HSADC for continuous sampling of 4 analog channels with 1MSamples / per seconds (each). While all things regarding data transfer has been successfully managed, I'm struggling now with power supply (VDDIO:3.3V) noise coupling directly into HSADC samples. 

1. During DMA transfer of samples form internal SRAM  to external SDRAM - 6mV of voltage noise is created on +3.3V VDDIO. See noise in attached TEK scope figure.
2. This noise can be directly seen on HSADC samples. (My analog inputs: ADCHS0 and  ADCHS_NEG are shorted and noise free).  See captured HSADC samples on attached figure.
   
3. I put additional capacitors on VDDIO, and this improved HSADC immunity, which indicate that noise is coupled through power supply. However I was not able to remove problem completely.

My questions are following:

1. Does anybody know from which power domain or power pins HSADC is supplied? I can't find any explicit statement in manual or datasheet about it. Any additional information about HSADC internal voltage reference and its power supply?
2. Is there any guideline how to route PCB (analog lines, power supply, ) in order to get maximal HSADC performance? All can be found in datasheet is Table 45 ( 12-bit ADC signal interference ) , which I strictly follow, but it looks that this is far to small, especially if you compare with considerations given for ordinary 12-bit ADC chip?

I wish I was wrong, but form my observation, it looks, that HSADC is supplied from digital power supply, and is very prone to digital power supply noise, and this make him practically unusable for some serious applications, as it's almost impossible to protect digital power supply form noise.

Regards, 

Irvin

[hmyoong]

Dear Irvin:

  Could you share with us on your experience to use LPC4370  for HSADC and external SDRAM?  If the LPC-Link2 comes with a lot of external SDRAM, then it would be very useful.

[Carlos_Mendoza]

Hi Irvin,

You can't really avoid these effect on systems running with high speed signals. You can only try to limit them to an acceptable level.

For noise on the power supply domains:
- Use more than one decoupling capacitor on each pin to reduce ESR
- Use filter circuits to get rid of specific frequencies

For crosstalking problems and frequency related problems

- Reduce the on-chip frequencies as much as you can. There is no need to run the CPU on 204MHz if you only need a 120MHz performance
- Reduce the current consumption of the MCU by switching off all blocks which are not needed
- Take care of the routing of the high speed signals (for example EMC) on the PCB
- Implement series resistors in the EMC signals (and maybe other fast digital interfaces) to reduce frequency responses
- Don't configure pins to high speed mode if not really required

Another quite tricky hint:  in the LQFP package definitions you can see on which side of the silicon die the AD converter(s) are located. The signals nearby the AD pins are the most suspicious to couple "noise" into the analog ports. On the BGA package these suspicious pins can normally also be founded in the same section of the chip, also the bondwires from the die to the ball locations are structures the same way. So, if you can, try to avoid using these pins by finding the required function on another pin (if available).

Hope it helps!

Best Regards,
Carlos Mendoza
Technical Support Engineer