Content originally posted in LPCWare by Rsing.Yang on Thu May 29 20:41:33 MST 2014
Thank you for the reply.
The code below is the ISR of M0 Enternet interrupt.
I use a globle variable _ints_ to record the value of DMA_STAT register .
_ints_ = 0x8010
That means bit:DMA_ST_OVF & bit:AIS of DMA_STAT register is set.But I don't know why and how this happens.
Is there any register that needs a special setting?Because I use the same setting as M4(Including device initialization/register setting/ISR). The most difference is they use different IRQ number and IRQ priority.
Do I need to run the initial funtcion in M4 ?
/**
* @briefEMAC interrupt handler
* @returnNothing
* @noteThis function handles the transmit, receive, and error interrupt of
* the LPC118xx/43xx. This is meant to be used when NO_SYS=0.
*/
#ifdef CORE_M0
void M0_ETH_IRQHandler(void)
#else
void ETH_IRQHandler(void)
#endif
{
signed portBASE_TYPE xRecTaskWoken = pdFALSE, XTXTaskWoken = pdFALSE;
uint32_t ints;
extern uint32_t _ints_; //a globle value
/* Get pending interrupts */
ints = LPC_ETHERNET->DMA_STAT;
_ints_ = ints; //record the value of DMA_STAT
/* RX group interrupt(s) */
if (ints & (DMA_ST_RI | DMA_ST_OVF | DMA_ST_RU)) {
/* Give semaphore to wakeup RX receive task. Note the FreeRTOS
method is used instead of the LWIP arch method. */
xSemaphoreGiveFromISR(lpc_enetdata.RxSem, &xRecTaskWoken);
}
/* TX group interrupt(s) */
if (ints & (DMA_ST_TI | DMA_ST_UNF | DMA_ST_TU)) {
/* Give semaphore to wakeup TX cleanup task. Note the FreeRTOS
method is used instead of the LWIP arch method. */
xSemaphoreGiveFromISR(lpc_enetdata.TxCleanSem, &XTXTaskWoken);
}
/* Clear pending interrupts */
LPC_ETHERNET->DMA_STAT = ints;
ints = LPC_ETHERNET->DMA_CURHOST_REC_BUF;
/* Context switch needed? */
portEND_SWITCHING_ISR(xRecTaskWoken || XTXTaskWoken);
}
