LPC4357 Core M0 features

[lpcware]

Content originally posted in LPCWare by DT1 on Tue Apr 01 13:40:27 MST 2014
Hi,

I'm not sure I understand perfectly what is shared between the M4 and M0 and what is specific. According to the user manual, almost everything is shared between the 2 cores by the matrix, but I still have some interrogations...

[list]
  [*]Is the FPU available to the core M0 (through the LPC4357 overall core) of it's only available to the core M4?
  [*]If I use an external SDRAM in both cores through EMC (not at the same time), must I do something special in the M0? I'm asking because I'm under the impression that accessing the SDRAM from the M0 is a little slower than from the M4. Must I enable a specific clock or configure a specific clock related to the M0?
  [*]Is the M0 clock automatically enabled or must I do something special to ensure it is running at the same frequency than my M4 (156MHz)?
[/list]

My current CGU init is like this:

uint32_tCGU_Init(void)
{
uint32_t idx = 0;

CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M4);

// Wait 100us
for (idx = 0; idx < 10000; ++idx);

CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
//CGU_SetPLL1(6);// 72 MHz
//CGU_SetPLL1(10);// 120 MHz
CGU_SetPLL1(13);// 156 MHz
//CGU_SetPLL1(16);// 192 MHz

CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);

CGU_UpdateClock();
return 0;
}

Followed later on by the SDRAM init function:

 LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
  while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
...
  div = 0;
  if (SystemCoreClock > 120000000UL) {
    /* Use EMC clock divider and EMC clock output delay */
    div = 1;
    /* Following code must be executed in RAM to ensure stable operation      */
    /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
    /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));                           */

    /* This code configures EMC clock divider and is executed in RAM          */
    for (n = 0; n < emcdivby2_szw; n++) {
      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
    }
    __ISB();
    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
    for (n = 0; n < emcdivby2_szw; n++) {
      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
    }
  }

Thanks!

[lpcware]

Content originally posted in LPCWare by DT1 on Mon Apr 07 10:58:35 MST 2014
Thanks a lot again. I have all I need to know now :)

[lpcware]

Content originally posted in LPCWare by bavarian on Thu Apr 03 03:15:10 MST 2014
Is the FPU available to the core M0 (through the LPC4357 overall core) of it's only available to the core M4?
--> it belongs to the Cortex-M4 exclusively. Using it even if no floating point values need to be handled increases the number of available core registers. This means that the compiler can decide to use these registers for stack purposes. This works a litte bit faster than doing it on the normal stack.

If I use an external SDRAM in both cores through EMC (not at the same time), must I do something special in the M0? I'm asking because I'm under the impression that accessing the SDRAM from the M0 is a little slower than from the M4. Must I enable a specific clock or configure a specific clock related to the M0?
--> The M4 and the M0 run on the same clock and have the same access rights.
      However: Their instruction set it different, an M3 or M4 core has a small buffer which belongs to the core (the M0 has not), it plays a role which bus is used (Data / Instruction / System) etc.
      So overall I don't wonder that the M0 performs slower than the M4


Is the M0 clock automatically enabled or must I do something special to ensure it is running at the same frequency than my M4 (156MHz)?
--> after reset the clock tree is fully configured for both cores, both are running on the same frequency

Regards,
NXP Support Team

[lpcware]

Content originally posted in LPCWare by rocketdawg on Wed Apr 02 07:51:48 MST 2014
the newest LPCOpen and LPCExpresso have working examples of dual core projects.
Basically, the M4 starts first, then does some work to set up the M0.

http://support.code-red-tech.com/CodeRedWiki/CodeRedFAQ

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Tue Apr 01 14:12:22 MST 2014
To start with, this mcu has two cores. One is a cortex-m4 with an fpu, and the second is a cortex-m0. The fpu is an integral part of the core. So, no, it is not accessible from them m0.