LPC4350 Boot Pins P2_9, P2_8, P1_2, P1_1

[gregdunn]

We are using the LPC4350FET256 in a design which has been in production for several years and we have shipped several thousand devices.  The design normally boots from SPIFI but also has a jumper option to allow booting in DFU mode over USB0 for updating the SPIFI firmware image.  We recently received a return unit that would not boot up properly in SPIFI or DFU mode.  After examining the board, I determined that P1_1 was not being properly interpreted as being in a high logic level at reset which caused an unexpected boot mode to be entered.  The board uses a 10K resistor to pull P1_1 to 3.3V.  The user manual indicates that the internal pin pull up resistor is also enabled by default at reset which should reinforce the high logic level.  We have noticed that if we leave the board powered down for several hours and then power it up, sometimes P1_1 will follow the 3.3V supply up and everything works fine during power on.  If you power cycle the board multiple times after that with relatively short periods of no power, P1_1 seems to be held down below the high threshold and the board doesn't boot properly.  If we reduce the 10K pull up resistor to about 7.5K then P1_1 is held high enough to boot correctly every time.  We are using 2 external SRAM chips in this design so P1_1 is also used for the address bus EMC_A6 signal but that is all that P1_1 is connected to.  We have also noticed that the P2_8 signal that we feed from the jumper to select normal or DFU mode also exhibits this same issue.  A 10K resistor is also used in this case.  Reducing the 10K will solve this problem as well.  

As I mentioned before, we have shipped several thousand of these boards over the past 6 years or so.  To my knowledge, this is the first time we have seen this issue.  Our customer says that they have others behaving the same way periodically.  I will try to receive these boards and analyze them also if possible.  We could probably fix this one board by changing resistor values, but other good boards do not show that we are even close to being marginal.  P1_1 follows the power supply all the way up to 3.3 volts on power up.

I have attached a zip file with several scope pictures which illustrate this issue on the bad board as well as one pic from a good board.

Any ideas on what may be going on here or suggestions for further analysis?  We have not attempted to cut traces going to the SRAM yet but may try this to isolate the issue to the LPC4350. 

Thanks,

Greg Dunn  

[gregdunn]

1) The reason that I don't want to just change to a 7.5K pull-up is because the LPC4350 documentation specifies that the P1_1 line should have an internal pull-up resistor enabled by default at reset which should allow the line to easily be pulled up to 3.3 volts at the end of reset.  The spec sheet shows -62uA typical for the pull-up current.   All other boards we have tested show that P1_1 follows the 3.3 volt supply ALL THE WAY up on power up with the 10K.  Additionally these boards carry a UL approval for hazardous area installation and the bill of material is locked to the approved design.  Any design changes require significant time and cost for re-certification through UL.  This is the first board out of several thousand that we have seen this issue on.  I am mostly inquiring to see if there is some kind of known failure mode in the LPC4350 processor which could cause this.  

2) In this case, the boot pins (P1_1, P1_2, P2_8 and P2_9) are all shared and used as EMC address lines and are connected to the SRAM address inputs.  The SRAM chip should not get an any mode where these lines would be driven high or low by the SRAM, they are high impedance inputs to the SRAM.  In addition, we have circuitry that disables the SRAM CE input during reset.  I am not sure how a tri-state buffer would help in this case.  The SRAM chip seems to function normally when the board is forced to boot in the application.  We don't suspect the SRAM as being the issue.  As we proceed with our troubleshooting, we will probably cut the traces going to the SRAM just to rule it out completely as the cause.  

[Alice_Yang]

Hello,

OK , also recommend you cut the traces going to the SRAM  , pull up ISP pins to check.

BR

Alice

[Alice_Yang]

Hello ,

1)You said "If we reduce the 10K pull up resistor to about 7.5K then P1_1 is held high enough to boot correctly every time. ", so how about use this method. 

2)There is another suggestion from other thread， how about it:

In "ancient" times, SBC and microcomputer designs used tristate line buffers or multiplexers with separate /OE pin to decouple the MCU/processor.  Not sure if that would be an option for you.

https://community.nxp.com/t5/LPC-Microcontrollers/LPC54628-a-serious-problem-with-ISP-boot-pins-shar...