LPC4330 PLL1

[tomsaluzzo]

I’m having quite a bit of trouble changing the PLL1 clock frequency. Refer to the PLL1 Control Register on page 185 of the User Manual. Bit 11 is the “AUTOBLOCK” bit. I can’t find a description of this bit in the User Manual. What should this bit equal when I’m trying to change the BASE_M4_CLK frequency (see page 166 of the User Manual)?

[Carlos_Mendoza]

Hi Tom,

The AUTOBLOCK flag prevents glitches of the output clock when switching from one input clock to another. Glitches may otherwise occur depending on the phase relation of the old and new clock. It is recommended to always use autoblocking.

Hope it helps!

Best Regards,
Carlos Mendoza
Technical Support Engineer