LPC1853 Changing Heap & Stack Sizes

[lpcware]

Content originally posted in LPCWare by wcarlsen on Thu Mar 26 08:01:27 MST 2015
Looking in the startup.s file that Keil provides with their uVision 5 IDE for the LPC1853 it initializes the Heap to 0x400 and the stack to 0x200. So can I increase the heap size to like 100k or will that have some negative side effect?

My understanding of how the memory allocation with SRAM works (of which there is 136kB on the 1853 per the datasheet) is that the static and global variables start filling up the SRAM from the bottom and then the Stack starts filling up the SRAM from the top and moving downward. It is also my understanding that the Heap then sits on top of the static section and works its way up.

So if my understanding is wrong, please do correct me and perhaps point me to an article, book, etc. that I can read. I would appreciate the resources as I am pretty new to embedded programming and trying to get a better understanding of memory etc.

But if my understanding if correct, then wouldn't that mean that there is an insane amount of wasted SRAM at the moment? Becasue the 0x400 and 0x200 only account for like 1.5k of ram but the chip has 138k I believe.

The specific reason I am posting this is because I found a PDF about C design patterns I was reading the other night and there is one called first class ADT but it relies on malloc() which was returning null for me because I was running out of heap after several calls to malloc() because the structs I was using malloc() on were like 300 bytes each.

Thanks in advance for any help!
Wesley

[lpcware]

Content originally posted in LPCWare by wcarlsen on Thu Mar 26 10:20:23 MST 2015
Ok, that makes sense I assumed it was all one big block of memory but I see why you couldn't make it 100K if there are sections that max out at 40k. I am going to have to do some more reading of the datasheet and maybe try and go through and understand what every line of the start-up file does. It works as is, but I just don't like using code that I don't know what it's doing.

Thanks for the tips!

[lpcware]

Content originally posted in LPCWare by capiman on Thu Mar 26 08:52:30 MST 2015
I don't think you can use complete memory, because the SRAM areas are not connected to one big SRAM area, but with holes inside.
As far as I remember the biggest available area (not looked into details for LPC1853) is 40 kBytes, some others with 32 kBytes.
So you can put one into the 40 kBytes SRAM area, the other one to 32 kBytes SRAM area.
And put all remaining variables/function in SRAM into a third SRAM area? I don't know if all areas have the same speed if they are accessed by Core-M3 itself.