LPC17xx weak pull up max. current?

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LPC17xx weak pull up max. current?

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by ntipping on Wed Nov 20 03:24:25 MST 2013
Hi All,

Apologies - I think I've answered my own question. Looks as though from the data sheet that it's a maximum of 85uA over temperature for a Vin of 0V - equivalent to about 39k. I'll leave the original question as the points I make are still valid, and I'd be interested in other views:

The LPC1769 data sheet only appears to have typical specs for the port weak pull ups. Does anyone have a maximum over temperature? I am in the middle of designing the LPC1769 into an existing application so I need to achieve compatibility with boards already in production. This is an ethernet-based modular controller which has up to 34 IO lines which can be inputs or outputs (depending on the boards fitted). The system expects the reset condition to have all outputs at 0. With all pins in reset defaulting to inputs (sensible) but with weak pull ups (not so sensible) the reset state of pins destined to become outputs is potentially 1. This is a no-no in a system controlling moving parts. I can't tolerate overriding pull downs on 34 pins (don't have space) and in any case, this would make a nonsense of a low power design. Could be a show-stopper on using NXP for me, especially if M4's (next project) behave the same. I don't think I'm the first to be caught out by this behaviour. My only hope would be if the max. current under all conditions is less than the min. drive required to turn an output on.

Best Regards,

Nick Tipping
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fwjohnson
Contributor I

Thanks for responding Rolf, and for the advice.  I realize this was a pretty old thread...

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by ntipping on Mon Nov 25 09:06:17 MST 2013
Hi Xianghui Wang,

They are driving in effect - just not with the current that an output can source. They might be inputs on reset, but the pull ups will still source a current capable of generating a high output voltage if the load is sufficiently low (looks like 30uA typical at  2.3V - data sheet Fig 13). Checking through all the designs we have here, it looks as though the load is too high to generate a logic '1' level from the pull ups, so I may get away with it.

Best Regards,

Nick Tipping
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fwjohnson
Contributor I

Hello,

I am running into this same issue (using a LPC1315).  I'm new to this so please let me know if I'm missing something obvious.

As Nick says, the default GPIO pins are in effect driving a 1 after reset due to the weak pull-up, and that is a problem if the default is supposed to be an Input.  So I have 2 questions:

1)Why is defaulting to Input but with a pull-up a good CPU design?  I see why defaulting to Input is good.  Not being snarky, I'd really like to know.

2)The pins that my firmware eventually configures as outputs are in fact appearing as hi to my UDN2987 during reset.  What is the standard way to get around this? Is a pull-down the right way?  Is it the only way?

Thanks!

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rolfmeeser
NXP Employee
NXP Employee

An external pull-down resistor of 10k (or stronger) is indeed the appropriate way to override the internal pull-up in those cases where you must force a logic low level.

We should leave the "why" question to the philosophers.

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by xianghuiwang on Mon Nov 25 08:12:55 MST 2013
Hi, Nick,
Trying to understand your concern. The GPIOs are default to input high, they are not driving.
Thanks,
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