LPC1788 and external SDRAM

[lorenzogalbiati]

Hello,

for the first time I'm trying to use an external DRAM (IS42S16100H) with LPC1788 and I have error during test. I can't read what I write, I have always a small amount of bytes with a different value. EMC works at 36MHz, far away from the limit of 80MHz.

I use IAR for ARM; if I write every byte in debug mode step by step I can write every bytes but if I execute at full speed I have errors. I suppose some timing problem but I don't know what to change. Please help me with suggestion because If I fail this product for my catory I could be fired

This is my EMC init:

void Init_EMC(void)
{
PCONP_bit.PCEMC=1;
EMCCLKSEL_bit.EMCDIV=1;       // The EMC usa the clock CPU/2 = 72/2 = 36MHz.

SCS_bit.EMCRD=0;                   // Reset EMC for any type of chip reset (BOD, POR, software reset)
SCS_bit.EMCBC=0;                  // Burst enabled
SCS_bit.EMCSC=1;                   // no static memory


EMCDLYCTL=0x00000604;      // value to check.??

EMCControl_bit.E=1;                // Enable
EMCControl_bit.L=0;               // Normal mode
EMCControl_bit.M=0;             // Normal memory map

EMCConfig_bit.ENDIAN=0;     // Little endian

EMCDynamicConfig0_bit.MD=0;                // SDRAM
EMCDynamicConfig0_bit.AML=0x21;          // (Bank, Row, Column)
EMCDynamicConfig0_bit.AMH=0;             // 16 Mbit (1Mx16), 2 banks, row = 11, column = 8
EMCDynamicConfig0_bit.B=0;
EMCDynamicConfig0_bit.P=0;                   // Writes not protected

EMCDynamicRasCas0_bit.RAS=3;
EMCDynamicRasCas0_bit.CAS=3;

EMCDynamicReadConfig_bit.RD=1; // using EMCCLKDELAY (command delayed, clock out not delayed)

EMCDynamictRP_bit.tRP=NS_TO_CLKS(18);                 // trp
EMCDynamictRAS_bit.tRAS=NS_TO_CLKS(36);          // tras
EMCDynamictSREX_bit.tSREX=NS_TO_CLKS(60);      // txsr
EMCDynamictAPR_bit.tAPR=NS_TO_CLKS(18);          // trcd
EMCDynamictDAL_bit.tDAL=5;                                     //tdal 
EMCDynamictWR_bit.tWR=2;                                       // tdpl
EMCDynamictRC_bit.tRC=NS_TO_CLKS(54);            // trc
EMCDynamictRFC_bit.tRFC=NS_TO_CLKS(60);       // trc
EMCDynamictXSR_bit.tXSR=NS_TO_CLKS(60);        // txsr
EMCDynamictRRD_bit.tRRD=NS_TO_CLKS(12);        // trrd
EMCDynamictMRD_bit.tMRD=2;                                 // tMCD


//----------------------------- NOP ----------------------------------------
EMCDynamicControl_bit.CE=1;                                 // All clock enable=1
EMCDynamicControl_bit.CS=1;                                // CLKOUT runs continuosly
EMCDynamicControl_bit.SR=0;                               // Normal mode
EMCDynamicControl_bit.MMC=0;                           // Memory clock control enabled
EMCDynamicControl_bit.I=3;                                  // NOP

wait2(1000);                                                                 //1ms wait

//------------------------ PRECHARGE ALL------------------------------------
EMCDynamicControl_bit.CE=1;                                // All clock enable=1
EMCDynamicControl_bit.CS=1;                               // CLKOUT runs continuosly
EMCDynamicControl_bit.SR=0;                              // Normal mode
EMCDynamicControl_bit.MMC=0;                         // Memory clock control enabled
EMCDynamicControl_bit.I=2;                                 // PRECHARGE ALL

EMCDynamicRefresh_bit.REFRESH=1; // 1 x 16 = 16 CCLKs between SDRAM refresh cycles
wait2(1000);

//------------------------- AUTO REFRESH ----------------------------------

EMCDynamicRefresh_bit.REFRESH=35; // (0.032/2048)*36000000/16 pag.187 user manual
wait2(1000);

//------------------------- MODE REGISTER ------------------------------------
EMCDynamicControl_bit.CE=1;                     // All clock enable=1
EMCDynamicControl_bit.CS=1;                    // CLKOUT runs continuosly
EMCDynamicControl_bit.SR=0;                  // Normal mode
EMCDynamicControl_bit.MMC=0;             // Memory clock control enabled
EMCDynamicControl_bit.I=1;                       // MODE command

dwTemp=*((WORD*)0xA000CC00);
wait2(1000);

//--------------------------- NORMAL MODE ------------------------------------
EMCDynamicControl_bit.CE=1;                  // All clock enable=1
EMCDynamicControl_bit.CS=1;                 // CLKOUT runs continuosly
EMCDynamicControl_bit.SR=0;                // Normal mode
EMCDynamicControl_bit.MMC=0;           // Memory clock control enabled
EMCDynamicControl_bit.I=0;                   // NORMAL

wait2(1000);                                                  //1ms delay

EMCDynamicConfig0_bit.B=1;                  //enable output buffer
}

Best regards.

[Harry_Zhang]

Hi @lorenzogalbiati 

I think you can refer to the 1788 LPCOPEN memtest demo.

You DRAM is IS42S16100H. And the LPCOPEN demo is used the IS42S32800D.

They are similar.

/* Keil SDRAM timing and chip Config */
STATIC const IP_EMC_DYN_CONFIG_T IS42S32800D_config = {
	EMC_NANOSECOND(64000000 / 4096),
	0x01,				/* Command Delayed */
	3,					/* tRP */
	7,					/* tRAS */
	EMC_NANOSECOND(70),	/* tSREX */
	EMC_CLOCK(0x01),	/* tAPR */
	EMC_CLOCK(0x05),	/* tDAL */
	EMC_NANOSECOND(12),	/* tWR */
	EMC_NANOSECOND(60),	/* tRC */
	EMC_NANOSECOND(60),	/* tRFC */
	EMC_NANOSECOND(70),	/* tXSR */
	EMC_NANOSECOND(12),	/* tRRD */
	EMC_CLOCK(0x02),	/* tMRD */
	{
		{
			EMC_ADDRESS_DYCS0,	/* EA Board uses DYCS0 for SDRAM */
			2,	/* RAS */

			EMC_DYN_MODE_WBMODE_PROGRAMMED |
			EMC_DYN_MODE_OPMODE_STANDARD |
			EMC_DYN_MODE_CAS_2 |
			EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
			EMC_DYN_MODE_BURST_LEN_4,

			EMC_DYN_CONFIG_DATA_BUS_32 |
			EMC_DYN_CONFIG_LPSDRAM |
			EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS |
			EMC_DYN_CONFIG_MD_SDRAM
		},
		{0, 0, 0, 0},
		{0, 0, 0, 0},
		{0, 0, 0, 0}
	}
};

BR

Harry

[lorenzogalbiati]

Hello,

thank you for the support. I have checked my code and now it works.

I had to change the delay for the "command delay" mode.

Best regards.