Hello again,
This is a picture with the output on the screen.
I am trying to write "Hello World" just once - but appears twice, 3 times ...
All day I checked the lines again. I connected pin 34 (Data Enable) to GND. As mentioned in datasheet at page 8 - "DE signal is fixed low for SYNC mode ".
Now vsync and hsync has an impact (when changed in code). Also pulse moves the image up/down, right / left.
I still have the problem (always did) wit that tearing / double / triple content. I am in progress of troubleshooting the SDRAM.
Please remember I have a single external SDRAM module, NOT 2. I searched everywhere , and seems that 2 x 16 bit modules are needed for LCD , but I would love to make this work as it is.
After the picture I've attached the source code for SDRAM init. I am sure I will be asked about it ...
Thankyou again.
Popte.
#define EMC_NS2CLK(ns, nsPerClk) ((ns + nsPerClk - 1) / nsPerClk)
#define tCLK_ns ((double)EMCClock / 1000000000.0 ) // CCLK periods in ns
volatile uint32_t ringosccount[2] = {0,0};
#define MDKCFG_RASCAS0VAL 0x00000303
#define MDKCFG_RASCAS1VAL 0x00000303
void EMC_GPIO_Init (void)
{
// (ok comment - means I checked the line with a multimeter / oscilloscope)
LPC_IOCON->P2_16 = 0x00000021; /* CASN @ P2.16 */ //ok CAS
LPC_IOCON->P2_17 = 0x00000021; /* RASN @ P2.17 */ //ok RAS
LPC_IOCON->P2_18 = 0x00000021; /* CLK[0] @ P2.18 */ //ok CLK
LPC_IOCON->P2_20 = 0x00000021; /* DYCSN[0] @ P2.20 */ //ok CS
LPC_IOCON->P2_24 = 0x00000021; /* CKE[0] @ P2.24 */
LPC_IOCON->P2_28 = 0x00000021; /* LDQM[0] @ P2.28 */
LPC_IOCON->P2_29 = 0x00000021; /* UDQM[1] @ P2.29 */
LPC_IOCON->P3_0 = 0x00000021; /* D0 @ P3.0 */ //ok
LPC_IOCON->P3_1 = 0x00000021; /* D1 @ P3.1 */ //ok
LPC_IOCON->P3_2 = 0x00000021; /* D2 @ P3.2 */ //ok
LPC_IOCON->P3_3 = 0x00000021; /* D3 @ P3.3 */ //ok
LPC_IOCON->P3_4 = 0x00000021; /* D4 @ P3.4 */ //ok
LPC_IOCON->P3_5 = 0x00000021; /* D5 @ P3.5 */ //ok
LPC_IOCON->P3_6 = 0x00000021; /* D6 @ P3.6 */ //ok
LPC_IOCON->P3_7 = 0x00000021; /* D7 @ P3.7 */ //ok
LPC_IOCON->P3_8 = 0x00000021; /* D8 @ P3.8 */ //ok
LPC_IOCON->P3_9 = 0x00000021; /* D9 @ P3.9 */ //ok
LPC_IOCON->P3_10 = 0x00000021; /* D10 @ P3.10 */ //ok
LPC_IOCON->P3_11 = 0x00000021; /* D11 @ P3.11 *///ok
LPC_IOCON->P3_12 = 0x00000021; /* D12 @ P3.12 */ //ok
LPC_IOCON->P3_13 = 0x00000021; /* D13 @ P3.13 */ //ok
LPC_IOCON->P3_14 = 0x00000021; /* D14 @ P3.14 */ //ok
LPC_IOCON->P3_15 = 0x00000021; /* D15 @ P3.15 */ //ok
LPC_IOCON->P4_0 = 0x00000021; /* A0 @ P4.0 */ //ok
LPC_IOCON->P4_1 = 0x00000021; /* A1 @ P4.1 */ //ok
LPC_IOCON->P4_2 = 0x00000021; /* A2 @ P4.2 */ // ok
LPC_IOCON->P4_3 = 0x00000021; /* A3 @ P4.3 */ // ok
LPC_IOCON->P4_4 = 0x00000021; /* A4 @ P4.4 */ // ok
LPC_IOCON->P4_5 = 0x00000021; /* A5 @ P4.5 */ //ok
LPC_IOCON->P4_6 = 0x00000021; /* A6 @ P4.6 */ //ok
LPC_IOCON->P4_7 = 0x00000021; /* A7 @ P4.7 */ //ok
LPC_IOCON->P4_8 = 0x00000021; /* A8 @ P4.8 */ //ok
LPC_IOCON->P4_9 = 0x00000021; /* A9 @ P4.9 */ //ok
LPC_IOCON->P4_10 = 0x00000021; /* A10 @ P4.10 */ //ok
LPC_IOCON->P4_11 = 0x00000021; /* A11 @ P4.11 */ //ok
LPC_IOCON->P4_12 |= 0x00000021; // BA0 //ok
LPC_IOCON->P4_13 |= 0x00000021; // BA1 //ok
LPC_IOCON->P4_25 = 0x00000021; /* WEN @ P4.25 */
}
void SDRAM_Init (void)
{
uint32_t i, dwtemp = dwtemp;
uint16_t wtemp = wtemp;
uint32_t mhz, nsPerClk;
/* Enable External Memory Controller power/clock */
LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL = 0x00001010;
//LPC_SC->EMCCLKSEL=0; //60 MHZ
LPC_SC->EMCDLYCTL = 0x00080808;
LPC_EMC->Control = 0x00000001;
LPC_EMC->Config = 0x00000000;
EMC_GPIO_Init();
mhz = SystemCoreClock / 1000000;
LPC_EMC->DynamicConfig0 = 0x00000480; /* 128B, 8Mx16, row=12, 4 banks, column=9 */
//Timing for 120MHz Bus: 8.333333 ns/clk
LPC_EMC->DynamicRasCas0 = 0x00000302; // 3 RAS, 3 CAS latency */
LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
LPC_EMC->DynamicRP = 0x00000003; // Min 20ns. (n + 1) -> 3 clock cycles
LPC_EMC->DynamicRAS = 0x00000006; // Min 44 ns.(n + 1) -> 6 clock cycles
LPC_EMC->DynamicSREX = 0x0000000A; // Min 75 ns. ( n + 1 ) -> 10 clock cycles */
LPC_EMC->DynamicAPR = 0x00000005; // ??? ( n + 1 ) -> 2 clock cycles */
LPC_EMC->DynamicDAL = 0x00000006; // tWR + tRP: min 35 ns (n + 1) -> 5 clock cycles */
LPC_EMC->DynamicWR = 0x00000002; // Min 15 ns. ( n + 1 ) -> 2 clock cycles */
LPC_EMC->DynamicRC = 0x00000008; // Min 66 ns. ( n + 1 ) -> 8 clock cycles */
LPC_EMC->DynamicRFC = 0x00000008; // Min 66 ns. ( n + 1 ) -> 8 clock cycles */
LPC_EMC->DynamicXSR = 0x0000000A; // Min 75 ns. ( n + 1 ) -> 10 clock cycles */
LPC_EMC->DynamicRRD = 0x00000002; // Min 15 ns. ( n + 1 ) -> 2 clock cycles */
LPC_EMC->DynamicMRD = 0x00000002; // 2 tCK. ( n + 1 ) -> 2 clock cycles */
for (i=0;i<200000;i++){LPC_EMC->DynamicControl = 0x00000183;}
delayMs(0, 100);
LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
delayMs(0, 200);
LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
//Timing for 120MHz Bus
LPC_EMC->DynamicRefresh = 0x2E;
LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
//Timing for 48/60/72MHZ Bus
dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x33<<(12)))); /* 8 burst, 3 CAS latency */
LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */
//[re]enable buffers
LPC_EMC->DynamicConfig0 |= 0x00080000; // Buffer enable
//TIM_Waitms(100);
}
Hi,
According to the AS4C8M16SA's datasheet, it's a 16-bit wide memory whose row and column length is 12 and 9 respectively.
So in my opinion, it should be configured as the following figure shows.
Have a great day,
TIC
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