LPC1788 2x SDRAM chips

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Imagineme on Tue Dec 04 03:21:56 MST 2012
Hi, i have the following idea/question. I`m designing my own development board based on lpc1788 and i want to connect 1 SDRAM chip(MT48LC16M16A2P 256M (16Mx16)) and leave traces and pads on the PCB for connection a second one (the same). My question is the following can i configure them to work in 16 bit manner, because i find same connections in which the 1st memory takes data lines 0:15 and the 2nd 16:31 but, this configuration has different Address line in 32-bit wide bus the address lines start from A2 and in 16-bit wide they start form A1.So i`m wondering if i can connect data lines 0-15 to both SDRAM chips and use the separate EMC_DYCS0; EMC_DYCS1 EMC_CKE0 EMC_CKE1 EMC_CLK0 EMC_CLK1 EMC_DQM0 and EMC_DQM1 to access them them in 16 bit manner. Thanks for your time.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by wella-tabor on Fri May 17 06:25:27 MST 2013
Hi,

this is my topic to these discussions, MT48LC4M32B2B5. It can be running at 120MHz but this is at the room temperature. The note about datasheet is right, there is stated "min 12,5 ns". Let's see.

Martin

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Dave on Wed May 15 15:49:43 MST 2013

Hi Martin,

It's funny you should mention this subject...

There have been a few discussions about this (see list below), and although NXP sticks by their claim that the part cannot exceed 80Mhz on the EMC, a lot of engineers seem to be doing just that.

I finally decided to just take it under advisement, since all of the boards I have built to date have been running at 120Mhz, and I haven't had a failure...

Here's an incomplete list of some of the discussions:

http://www.keil.com/forum/19185/

http://lpcware.com/content/forum/sdram-working-prototype-not-production

http://lpcware.com/content/forum/emc-clock

Feel free to add more to this discussion. ;-)

lpcware · ‎06-15-2016

Content originally posted in LPCWare by wella-tabor on Tue May 14 01:44:52 MST 2013

Hello,

<em>BTW, the max clock speed for SDRAM is 80Mhz, so if you run the cpu at more than this,</em>
<em> you have to select emc clock as cpu clk / 2. I.e if you run cpu at 120 MHz, the mem</em>
<em> needs to be set up for a 60 MHz clock.</em>

I saw this note in many threads but I cannot find any note in the Datasheet or UM. Anyway my CPU runs at 120MHz without any divider(1/2) for the SDRAM. It passes the March B, C tests. Do you mean some particular SDRAM or in generally?

Best

Martin

lpcware · ‎06-15-2016

Content originally posted in LPCWare by alimicro on Mon May 13 12:05:27 MST 2013

Hi have used below address as a reference for EMC:

<a href="http://www.embedinfo.com/en/list.asp?id=107">http://www.embedinfo.com/en/list.asp?id=107</a>

in this schematic have used 2xMT48lc16m16 which is obtain 64MB in 32bit structure.

I'am trying to change the CMSIS sample codes for OEM509 board but I can't

here is the SDRAMInit code:

<h4>void SDRAMInit( void )</h4>
<h4>{</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>volatile uint32_t i;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>volatile unsigned long Dummy;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_16 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_17 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_18 = 0x21;</h4>
<h4> </h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_19 = 0x21;</h4>
<h4> </h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_20 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_24 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_28 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_29 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_30 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P2_31 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_0 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_1 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_2 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_3 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_4 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_5 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_6 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_7 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_8 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_9 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_10 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_11 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_12 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_13 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_14 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_15 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_16 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_17 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_18 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_19 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_20 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_21 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_22 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_23 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_24 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_25 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_26 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_27 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_28 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_29 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_30 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P3_31 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_0 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_1 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_2 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_3 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_4 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_5 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_6 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_7 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_8 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_9 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_10 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_11 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_12 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_13 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_14 = 0x21;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_IOCON->P4_25 = 0x21;</h4>
<h4> </h4>
<h4> </h4>
<h4> </h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>//<span class="Apple-tab-span" style="white-space: pre;"> </span>EMC_Init();</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// Init SDRAM controller</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_SC->PCONP <span class="Apple-tab-span" style="white-space: pre;"> </span>|= 0x00000800;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>/*Init SDRAM controller*/</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_SC->EMCDLYCTL |= (8<<0);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>/*Set data read delay*/</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_SC->EMCDLYCTL |=(8<<8);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_SC->EMCDLYCTL |= (0x08 <<16);</h4>
<h4> </h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->Control =1;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicReadConfig = 1;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRasCas0 = 0;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRasCas0 |=(3<<8);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRasCas0 |= (3<<0);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRP = P2C(SDRAM_TRP);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRAS = P2C(SDRAM_TRAS);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicSREX = P2C(SDRAM_TXSR);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicAPR = SDRAM_TAPR;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicDAL = SDRAM_TDAL+P2C(SDRAM_TRP);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicWR = SDRAM_TWR;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRC = P2C(SDRAM_TRC);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRFC = P2C(SDRAM_TRFC);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicXSR = P2C(SDRAM_TXSR);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRRD = P2C(SDRAM_TRRD);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicMRD = SDRAM_TMRD;</h4>
<h4> </h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// 13 row, 9 - col, SDRAM</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicConfig0 = 0x0004680;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// JEDEC General SDRAM Initialization Sequence</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// DELAY to allow power and clocks to stabilize ~100 us</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// NOP</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicControl = 0x0183;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>for(i= 200*30; i;i--);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// PALL</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicControl = 0x0103;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRefresh = 2;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>for(i= 256; i; --i); // > 128 clk</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicRefresh = P2C(SDRAM_REFRESH) >> 4;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// COMM</h4>
<h4> </h4>
<h4> LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>Dummy = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x32<<13)));</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>// NORM</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicControl = 0x0000;</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>LPC_EMC->DynamicConfig0 |=(1<<19);</h4>
<h4><span class="Apple-tab-span" style="white-space: pre;"> </span>for(i = 100000; i;i--);</h4>
<h4> </h4>
<h4>}</h4>

with such a source code controller can write values less than 0x200000

above that it will be crazy. here is part of source code:

<h3>wr_ptr = (uint32_t *)SDRAM_BASE_ADDR;</h3>
<h3>*wr_ptr = 0xFFFF0A0A;</h3>
<h3>v1=(unsigned long)(*wr_ptr);</h3>
<h3>*wr_ptr = 0x00000012;</h3>
<h3>v2=(unsigned long)(*wr_ptr);</h3>
<h4>and results are:</h4>
<h4>v1=0x88C9760A</h4>
<h4>v2=0x00000012</h4>

the datasheet is so mysterious and there is no forum and no discussion about it.

please help me

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Dave on Tue Dec 11 09:46:37 MST 2012
That's why I left ST Micro... (and will never use their parts again!)

But I have to say, although NXP doesn't have a repository full of everything possible on each and every part they make, they do have a lot of documentation - you just have to do some digging to find it...

Combining this with the generalized documentation available from Freescale and Micron, it wasn't too difficult to get my first prototype up and running...

Although, I have to admit I was only about 50% confident until I actually got code written for it and ran some tests.

Sure would be nice to go back to the days when user's manuals had everything you could possibly want in them...

lpcware · ‎06-15-2016

Content originally posted in LPCWare by MikeSimmonds on Tue Dec 11 00:18:27 MST 2012
I Totally agree!

Warning -- this is a bit of a rant against NXP and other chip companies!
Please ignore/skip if you don't like frank comment.

NXP (and the others) want to make money.
To do this they need to sell chips.

Consumers will only buy chips that:
(1) have the features they need for their project.
(2) that they know how to develop with.

(1) is down to market reasearch, user feedback, watching competitors.
(2) NEEDS good clear COMPLETE well indexed documentation!

BAD/INADEQUATE DOCUMENTATION HITS YOUR BOTTOM LINE!

And because the devices are becoming increasing complex, we
need detailed (even cookbook level) application notes
RELEVANT to the part in question.

If NXP want to promote their devices even more, Backgrounder
articles need to be written. Accurate (debugged) sample code
is a must.

And remember to cover the 'corner cases'.

E.g. SDRAM interfacing is highly complex; it is one thing
to have bits in device registers that select 'command delayed'
strategy or 'clock out delayed' strategy.
But what the heck are these, why would a developer choose one
over the other, what do they ACTUALLY do?

The UM is totally silent on this -- developers NEED app notes
and backgrounders or they won't know how to develop with the device
and so won't buy it!

PCB designers need other equally vital information.

If silicon bugs come to light -- PLEASE acknowledge these
quickly and explicitly. Almost all developers will not hold
this against the company, but can use a work round, or it may
not be relevent in their current project.
It saves them wasted time and frustration (sometimes to the point
that they abandon YOUR device and go with a rival -- bottom line
again!)

Also note the Purchase departments in companies are usually technically
ignorent -- it is the engineers that require this or that chip to be
purchased.

Initial orders WILL be small (less than 10, 5) for evaluation etc.
If the documentation/app notes/example code is sub-standard, NO MORE
chips will be bought!

But if the documentation and related matter are excelent, many more
devices are purchased for the sucessful project's lifespan.

Finally, remember that today's hobyist/student is very soon tomorrow's
engineer; their experience then will translate to YOUR devices being
recommended rather than a competitors with better documantation.

Thanks for listening. Mike

PS: NXP staff, bump this up the food chain if at all possible.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Imagineme on Fri Dec 07 00:49:36 MST 2012
I have exactly the same feeling, when i was designed a board based on analog devices ADSP-21489 there was information about everything u just had to find and read.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by SimonThome on Thu Dec 06 10:58:08 MST 2012
I would very much like to see a detailed application note from NXP from this family of MCUs for the SDRAM. Detailing various configurations and more importantly their recommended PCB layout and stack-up recommendations starting with 4 layer PCBs, including the LQFP packages!

I feel like I’m designing somewhat blindly here, even though I have used ideas from various other app notes.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Imagineme on Thu Dec 06 05:52:58 MST 2012
Thank you for the detailed info.U both have been very helpful thanks again best of luck to both of you.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by MikeSimmonds on Wed Dec 05 11:36:53 MST 2012
Thanks for the correction Rolf; I hadn't realised that the clock enables were aligned with the dynamic chip selects.
(Mea culpa)
Mike

lpcware · ‎06-15-2016

Content originally posted in LPCWare by DF9DQ on Wed Dec 05 03:15:00 MST 2012
That's an almost complete run-down on SDRAM connections, so I will only add two minor remarks :-)

The CKEOUTx signals are paired with the DYCSx signals. So if you choose the two chip select option, you must use DYCS0/CKEOUT0 for one device, and DYCS1/CKEOUT1 for the second one. The clock can be common for both.

If you choose the 32-bit single chip select version, I think you still have the option of using only one device. Software configuration will be different of course, but the hardware connection of the SDRAM device at D0...D15 is the same, whether you have a second device at D16..D31 or not.

Regards,
Rolf

(I've edited this post, because originally I referred to a signal of the LPC43xx...)

lpcware · ‎06-15-2016

Content originally posted in LPCWare by MikeSimmonds on Tue Dec 04 23:20:29 MST 2012
First of all the user manual is no bloody help at connecting SDRAM at all!
Download and read AN10935.pdf from NXP site (search). This is for an ARM9
device with a slightly different EMC controller but it has much better background.

Second on the 1778/1788 you MUST connect A0 to A12 (from the CPU) to A0 to A12
on any and all SDRAM parts (1 or more) [Maybe A0 to A11 or A10 on smaller SDRAM chips,
but up to A12 for the Micron MT48LC16M16 devices]
Also you MUST connect A13 cpu to BA0 mem and A14 cpu to BA1 mem. The UM really sucks
about explaining this -- cost us 500 euro in useless PCB's!

Don't worry about A0/A1 for 16 bit/32 memory, the cpu takes the address asked for in
a read or write operation and puts the correct signals as required on these hardware
pins. [AN10935 gives a bit of background -- or you can just take it as what you have to do.]

Now -- data bus width.
You can choose to send D0-D15 (and DQM0/1) to one chip and D16-D31 (and DQM2/3)to the other
and configure your io pins and SDRAM setup for a 32bit wide data bus (and one chip select)
OR
D0-D15 (and DQM0/1) to BOTH chips and have a 16 bit data bus (and two chip selects)

For the second case, you can use the same SDRAM Clock (and enable) on both chips or use
the second pair for the other chip. The main difference is that one chip is not being
clocked while you access the other and you save a smidgeon of power.

Given the EMC CLOCK DELAY, I would sugesst using CK0/CKE0 for both regardless of 16 or 32
bit data bus.

Obviously, if you opt for the faster 32bit bus, you have to fit both chips up front.
In the 16bit bus case, you don't have to fit the second chip unless you want the
extra memory. (Presumeably with a slight change to the SDRAM init code.)

That's for the hardware PCB connections, obviously, your code to setup will vary a bit
depending which tracking choices you make -- also read the app note about 'Row-Bank-Column'
as opposed to 'Bank-Row-Column'

Search this forum (17xx) for SDRAM and EMC for sample code, and other SDRAM issues.

BTW, the max clock speed for SDRAM is 80Mhz, so if you run the cpu at more than this,
you have to select emc clock as cpu clk / 2. I.e if you run cpu at 120 MHz, the mem
needs to be set up for a 60 MHz clock.

Hope this helps. Mike.

LPC1788 2x SDRAM chips

LPC1788 2x SDRAM chips

LPC17xx