LPC1778, SDRAM, & EMC - Basic questions & a possible board design problem

[lpcware]

Content originally posted in LPCWare by wheels on Wed Dec 02 16:33:32 MST 2015
I've been given a design for a proposed board using an LPC1778 and an AS4C4M16SA SDRAM chip. I've never used SDRAM before, so I'm having some problems figuring things out.

The first problem is that the SDRAM is 1Mx16x4 banks, which isn't listed in Table 133 of the EMC chapter of UM10470 as a supported configuration for address mapping. Does this mean that the SDRAM won't work at all? What happens if I configure the EMC for 4Mx16x4 banks? Will the device be mapped four times in the address space? I'm presuming that if that's possible, it's better than trying to configure for 1Mx16x2 banks, but I don't know.

Second, presuming I can actually use this SDRAM device, how do I determine the register values for the EMC? It has a bunch of programmable parameters (tRP, tAPR, tDAL, tRC, etc.), but the SDRAM's data sheet only gives me tCK3 (minimum clock cycle time), tAC3 (max access time from clock), tRAS (row active time), and tRC (row cycle time). Is it likely to work if I leave them all at their defaults?

Any help will be greatly appreciated.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sun Dec 06 01:51:31 MST 2015
Here are a couple of macros (#defines) to help.

eClk in MHz, ns in nSec times ten.

#define eClk            (120/2)         // CPU clock is 120 MHz
#define ns2clk(ns)(((ns * eClk)+9999)/10000)

E.g.

tRP = ns2clk(200);       // tRP is 20.0 nano seconds
tWR = ns2clk(75);        // tWR is  7.5 nano seconds etc.

Note we must round UP.
And some of the EMC registers need you to subtract 1 (or 2) from the desired 'clock' value
(calculated by the macro) when writing to the register. (See UM.)

Cheers, Mike

[lpcware]

Content originally posted in LPCWare by wheels on Fri Dec 04 10:49:43 MST 2015
Thanks, Mike. I appreciate the help.

You're right, the board will have one device on a 16-bit bus. I'm now trying to reconcile Alliance's terminology with NXP's, and working up a spreadsheet to do the ns-to-cycles conversions for me to limit mistakes. Fun stuff, maybe.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Fri Dec 04 01:36:13 MST 2015
Yes -- look at the SDRAM datasheet title (just below the double line at the top of the page).
When refering to the address map table in the UM, your device has a 64 megaBIT capacity
arranged as 16 bits wide in 4 banks.

I assume that you only have one device on a 16 bit wide data bus.
[It is possible to put two 16-bit SDRAMs in a design with a 32 bit wide data bus.
Then the address mapping is slightly different.]

Cheers, Mike.

[lpcware]

Content originally posted in LPCWare by wheels on Thu Dec 03 09:19:08 MST 2015
Thanks. Don't know how I skipped past the table on page 19. Probably just lost in the stack of paper that includes all the other printouts on SDRAM and how to use it (I've found a lot of things I've printed out to study). Converting to clocks I knew about, I'd just missed seeing the other parameters listed anywhere.

I had already found that the address bit wiring was incorrect with respect to A13 and A14 and the bank select bits and had it corrected - there's a prior discussion here that made that very clear. Thanks for the additional verification, though.

As far as the organization of the part, I understand the 1M by 16 bits per each of 4 banks. My question related to the fact that the EMC doesn't appear list that as a supported configuration in table 133. Are you saying that the table entries that contain "64Mbit (4Mx16), 4 banks" are the ones I need to use? I was thinking that since the SDRAM data sheet had "1M word x 16-bit x 4-bank" listed under "Features," that "(1Mx16), 4 banks" was the important portion that I had to match in the EMC table. As you say, complicated. Not to mention, confusing.

Thanks again.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Thu Dec 03 04:06:51 MST 2015
For a start, look at page 19 of the data sheet (I Googled and Rev 1.0-63nm was the top hit) for the other parameters.
This is actually a 4M part, (1M is just for one bank). 64 Mbits (4Mx16) 4 Banks. NB: decide on row-bank-column or bank-row-column.

The data sheet values (in ns) have to be converted to EMC clock cycles (rounded up). And 1 or 2 subtracted (varies by
specific register). NB EMC clock max is 80 MHz, and can chose CPU clock or half CPU clock. This may limit the speed.
E.g. If CPU is at 120MHz, EMC must be 60MHz.

NOTE: Double check your address line connections -- this badly documented and confusing in the UM!

A0 to Ax (depends on rows+columns) go to A0..Ax on the device. See pinout in the SDRAM datasheet.
[Seems to be A0 to A11, but don't take my word for it.]
A13 and A14 (cpu) goto BA0 and BA1 on device. It is A13 and A14 regardless for the bank addresses!

See some of the NXP AppNotes AN10771, AN10935, AN10950, AN11508 and others.

This very complicated -- search the formus for SDRAM etc. and look at the LPCOpen samples.

Cheers, Mike.