LPC1769/LPCOpen: SPP Interface with Microchip SPI Flash

[spyros]

Greetings!

I'm trying to interface an SPI Flash memory from Microchip (SST25VF080B-50-4C; datasheet attached) using the SSP interface of the LPC1769 LPCXpresso board. I'm using the LPCOpen library. Initially I would like to issue simple blocking commands and get some fixed responses out of the chip. For instance issuing the JEDEC READ-ID command (0x9F; page 16) should return a fixed response of 3 bytes: [0xBF, 0x25, 0x8E]. However no matter what I do I'm getting [0xBE, 0x19, 0xF8]. Same thing happens with the Read Status Register command (0x05; page 14) which on powerup should return 0b00111000 (0x38); instead it returns 0b00011000 (0x18).

My connections are as follows

• Vdd: 3V3 and Vss: GND
• HOLD#: Driven HI; functionality not needed
• SCK: To LPC1769 SCK1 (p7)
• SO: To LPC1769 MISO1 (p6)
• SI: To LPC1769 MOSI1 (p5)
• WP#: Driven HI; software controlled
• CE#: To LPC1769 P0.28

I've connected CE# to a GPIO instead of SSEL1 since CE# seems to be pulled HI after every byte transferred instead at the end of the sequence. This causes the memory to reset the command.  Do you have any guidance on how to proceed? Of course it is entirely possible that I missed something fundamental, the newbie that I am. This is a snippet of my code so far. I've tried altering the SCK frequency to values from 100 kHz (default) up 24 MHz with the same results.

#include "board.h"
#define LPC_SSP     LPC_SSP1
/* The JEDEC READ-ID cmd */
static uint8_t JRDID[1] = { 0x9F };
/* Buffer to hold the 1 byte response */
static uint8_t rx_buf[1];

void print_buffer(uint8_t *buf, uint8_t len) {
    for (int i=0; i < len; i++) {
        char byte[16];
        sprintf(byte, "%x", buf[i]);
        DEBUGSTR(byte);
        DEBUGSTR(" ");
    }
    DEBUGSTR("\r\n");
}

int main(void) {
    SystemCoreClockUpdate();
    Board_Init();

    Chip_GPIO_SetPinDIROutput(LPC_GPIO, 0, 22);
    Chip_GPIO_SetPinDIROutput(LPC_GPIO, 0, 28); /* for CE */
    Chip_GPIO_SetPinState(LPC_GPIO, 0, 22, true);
    Chip_GPIO_SetPinState(LPC_GPIO, 0, 28, true);

    Board_SSP_Init(LPC_SSP);
    Chip_SSP_Init(LPC_SSP);
    ssp_format.frameFormat = SSP_FRAMEFORMAT_SPI; /* SPI */
    ssp_format.bits = SSP_BITS_8; /* 8 bits per frame */
    ssp_format.clockMode = SSP_CLOCK_MODE0; /* MODE0; CPHA=0; CPOL=0 */
    Chip_SSP_SetFormat(LPC_SSP, ssp_format.bits, ssp_format.frameFormat,
            ssp_format.clockMode);
    Chip_SSP_Enable(LPC_SSP);
    Chip_SSP_SetMaster(LPC_SSP, 1);

    /* Pull CE# LO */
    Chip_GPIO_SetPinState(LPC_GPIO, 0, 28, false);
    /* Write JRDID - 1 byte */
    Chip_SSP_WriteFrames_Blocking(LPC_SSP, JRDID , 1);
    /* Read 1 byte into rx_buf */
    Chip_SSP_ReadFrames_Blocking(LPC_SSP, rx_buf, 1);
    /* Pull CE# HI */
    Chip_GPIO_SetPinState(LPC_GPIO, 0, 28, true);
    print_buffer(rx_buf, 1);
}

I'm using separate WriteFrames and ReadFrames since they will clear the dummy read/write data from the FIFO. But the results are the same with the RW function.

[kerryzhou]

Hi Spyros Stathopoulos,

     Just check the code, it is not enough.

    Please find a Logic Analyzer to check the SPI bus wave, check the data on the SPI bus, make sure what the JEDEC READ-ID on the bus.

    Please check it at first, then send it to me.

    If the bus is really [0xBF, 0x25, 0x8E], but in the code it get [0xBE, 0x19, 0xF8], it will be the code problem.

   Please check the bus like this:

Then send the SPI bus wave to me.

 Your spi slave can support the SPI mode 0(0,0) and SPI mode 3(1,1), your LPC using SPI mode0, so it seems the mode don't have the problem.

Now, we need to check your SPI bus wave and the real data in the bus, then to do the deep analysis.

Have a great day,
Kerry

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[spyros]

Setting the clock to 500 kHz seems to have helped. I've attached the trace (x-axis is time in us) from the JEDEC READ-ID command the chip responds with the correct set of bits. This has also been confirmed by the software. At 600 kHz the output is similar to what I've observed in the original post.

I've also checked the Read Status Register command (RDSR). On powerup the chip responds with 0b00011100 (0x1C) which seems correct according to page 5 of the manual. Upon issuing the Write Enable command (WREN) when reading the status register again the bit 1 (starting from 0) is flipped and RDSR returns (0b0001110). This seems consistent with what the manual indicates. So it seems that the 600 kHz was affecting the outputs. I need to investigate what's the case in higher clock frequencies.

[kerryzhou]

OK， please also check the slave datasheet, whether 600khz clock sequence is meet that chip's demand.

You also can compare the 600Khz SPI wave with the 500Khz, except the frequency, any other difference, please also use the oscilloscope to check the 500Khz and 600Khz wave.

Have a great day,
Lerru

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