LPC1768 GPIO state DURING reset

[prakashbhumired]

Hi 

Our customer (Honeywell) has designed a product where "during" reset (not after reset), the GPIOs are settling to a high voltage (towards the Vdd/supply), due to which the interfaces are enabled accidentally "during" reset. They designed the application assuming the GPIO reset state is High-Z input.

Although, we have not reviewed their schematic and the actual environment, they would like to know the GPIO pin state 

"DURING" reset ( Is it High-Z, input with pull-up/pull-down etc?). Also would like to know the on-chip pull-up resistance/current value if the GPIO reset state is input with pull-up.

They need this information to calculate the external pull-up/down resistor/current in order to avoid inadvertent activation of interfaces DURING reset.

I tried to get the answer myself through communities, reference manual/datasheets, but no mention of this data.

This question should preferably go to the I/O designer of LPC1768 and kindly request to answer in relation to LPC1768.

Regards

Prakash

[Carlos_Mendoza]

Hi Prakash,

During reset the port pins will go from undefined state to input state with pull-up resistor. This takes place directly after the reset is active. The delay is around a few nsec.

About the pull-up and pull-down 'weaks', these are not actual resistors. They are transistors configured as a current source with a typical short circuit current of 50 uA. They are 'weak' current sources. For simplicity, we call them resistors.

See chapter 11.3 in the data sheet (Electrical pin characteristics). It has figures showing the V-vs-I characteristics of the pull-up/pull-down:

http://cache.nxp.com/docs/en/data-sheet/LPC1769_68_67_66_65_64_63.pdf

I would recommend you to enter a support request for your customer questions:

Support|NXP 

Hope it helps!

Best Regards,
Carlos Mendoza
Technical Support Engineer

[prakashbhumired]

Hi Carlos_Mendoza ,

Thank yoy very much quick and clear response.

Sorry, I will post customer questions on support from next time.

Few questions again:

1. So can I assume the effective resitance is equal to 3.3/50uA, just for an example and use it for pull down estimation? Is this a fair assumption?

2. A general question: I have gone through couple of NXP,Legacy FSL and competitor MCU datasheets, but never saw this "DURING reset" behaviour explicitly documented? Just  

    curious to know about this.

3. Is it the same state (input with pull-up), during "power on reset" (POR) as well ( during the defined clock cycles for the POR logic)?

Regards

Prakash

[Carlos_Mendoza · Accepted solution]

Hi Prakash,

You are welcome, answering your questions:

1.- You can use those values as an estimation but I would recommend you to test the pull-down resistor and its effectiveness.

2.- This information is mentioned in the Data sheet and User manual:

3.- The same applies for the POR, after reset the the port pins will go from undefined state to input state with pull-up resistor.

Hope it helps!

Best Regards,
Carlos Mendoza
Technical Support Engineer