LPC1768 + GPDMA + SSP + Burst size + memory boundary/alignment

[lpcware]

Content originally posted in LPCWare by solsal on Thu Aug 23 16:18:14 MST 2012
LPC1768 + GPDMA + SSP + Burst size + memory boundary
Hi,

please refer to UM10360 page:611

my question is around these items:

LPC1768 + GPDMA + Burst size + memory boundary/alignment

.................................................. .................................................. ...................

31.6.4 Address generation
Address generation can be either incrementing or non-incrementing (address wrapping is
not supported).
Some devices, especially memories, disallow burst accesses across certain address
boundaries. The DMA controller assumes that this is the case with any source or
destination area, which is configured for incrementing addressing. This boundary is
assumed to be aligned with the specified burst size. For example, if the channel is set for
16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is
address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then,
instead of a burst, that transfer is split into separate AHB transactions.

31.6.4.1 Word-aligned transfers across a boundary
The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a
destination for which address incrementing is enabled. The start address for the current
burst is 0x0C000024, the next boundary (calculated from the burst size and transfer
width) is 0x0C000040.
The transfer will be split into two AHB transactions:
• a 7-transfer burst starting at address 0x0C000024
• a 9-transfer burst starting at address 0x0C000040.

================================================== ====

1. what do those paragraphs mean?

2. Q: How should this operation be done?

I want to send an array of 1024 bytes to SSP0( spi ) and receive 1024 bytes from it to another array of 1024 bytes.
(send and receive are Simultaneous : this is a full duplex operation then which of M2P/P2M/M2M ???)

( this is repeatedly done every 100ms )

"SSP0(SPI) hardware is connected to another 8bit_uC_SPI"

by using SSP0+GPDMA+BURST+ "two 1024 bytes array in sram"

what is the exact solution for this question?

( I studied the USER MANUAL UM10360 but it is not clear enough and
I didn't find clean information around this )

================================================== ====

I have already done this operation on ( AT91SAM7X256(master) + atmega32(slave) ) on keil(arm) + codevision(AVR)....

now I want to do this by ( LPC1768(master) + atmega32(slave) ) , but this
GPDMA+BURST+memory alignment .... is confusing thing.

the slave device is working properly on previous design and I need to run Master(lpc1768) properly.

================================================== ====

please share your knowledge ,

regards.

www.nxp.com/documents/user_manual/UM10360.pdf

[lpcware]

Content originally posted in LPCWare by solsal on Sat Aug 25 23:44:36 MST 2012
SSP INTERRUPTS ?



Table 376: SSPn Raw Interrupt Status register (SSP0RIS - address 0x4008 8018, SSP1RIS -0x4003 0018) bit description

Bit  Symbol    Description                                                             ResetValue  Comment

0    RORRIS    This bit is 1 if another frame was completely received while the RxFIFO      0      error
               was full. The ARM spec implies that the preceding frame data is                     status
               overwritten by the new frame data when this occurs.

1    RTRIS     This bit is 1 if the Rx FIFO is not empty, and has not been read for a       0      error
               "timeout period". The timeout period is the same for master and slave               status
               modes and is determined by the SSP bit rate: 32 bits at PCLK /
               (CPSDVSR × [SCR+1]).

2    RXRIS     This bit is 1 if the Rx FIFO is at least half full.                          0      read RX fifo
                                                                                                  
3    TXRIS     This bit is 1 if the Tx FIFO is at least half empty.                         1      write to TX fifo
                                                                                                   till end of stream

31:4 - Reserved, user software should not write ones to reserved bits. The                  NA
                 value read from a reserved bit is not defined.

=========================================================================================================

how can we use these interrupts bits for a full_duplex byte_by_byte transfer in LPC1768 SSP(SPI) peripheral ?

=========================================================================================================

example problem:( send and receive some bytes (1-by-1) by SSP , using interrupt

1. I want to do this by interrupt mode , ( NO Polling the SR register , because of software overhead )
2. for receiving 1 byte from SSP ,I send 1 byte to SSP , then.... by which interrupt condition I will be warned
   that the receive or send byte is reached(done) ?


regards

[lpcware]

Content originally posted in LPCWare by solsal on Fri Aug 24 02:12:56 MST 2012
Hi,

reading the examples of code_bundle_lpc1768 available at nxp.com

SSP examples ( for keil )

sspdma.uvproj

=================================================================

uint32_t DMAChannel_Init( uint32_t ChannelNum, uint32_t DMAMode )
{
  if ( ChannelNum == 0 )
  {
SSP0DMADone = 0;
LPC_GPDMA->IntTCClear = 0x01<<0;
LPC_GPDMA->IntErrClr = 0x01<<0;  
if ( DMAMode == M2P )
{
  /* Ch0 set for M2P transfer from mempry to peripheral. */
  LPC_GPDMACH0->CSrcAddr = SSP0_DMA_TX_SRC;
  LPC_GPDMACH0->CDestAddr = SSP0_DMA_TX_DST;
  /* The burst size is set to 1, source and dest transfer width is
  32 bits(word), Terminal Count Int enable */
  LPC_GPDMACH0->CControl = (SSP_DMA_SIZE & 0x0FFF)|(0x00 << 12)
|(0x00 << 15)|(0x00 << 18)|(0x00 << 21)|(1 << 26)|0x80000000;
}
else if ( DMAMode == P2M )
{
  /* Ch0 set for P2M transfer from peripheral to memory. */
  LPC_GPDMACH0->CSrcAddr = SSP0_DMA_RX_SRC;
  LPC_GPDMACH0->CDestAddr = SSP0_DMA_RX_DST;
  /* The burst size is set to 1. Terminal Count Int enable. */
  LPC_GPDMACH0->CControl = (SSP_DMA_SIZE & 0x0FFF)|(0x00 << 12)
|(0x00 << 15)|(0x00 << 18)|(0x00 << 21)|(1 << 27)|0x80000000;
}
else
{
  return ( FALSE );
}
  }
  else if ( ChannelNum == 1 )
  {
SSP1DMADone = 0;  
LPC_GPDMA->IntTCClear = 0x01<<1;
LPC_GPDMA->IntErrClr = 0x01<<1;
if ( DMAMode == M2P )
{
  /* Ch1 set for M2P transfer from mempry to peripheral. */
  LPC_GPDMACH1->CSrcAddr = SSP1_DMA_TX_SRC;
  LPC_GPDMACH1->CDestAddr = SSP1_DMA_TX_DST;
  /* The burst size is set to 1. Terminal Count Int enable. */
  LPC_GPDMACH1->CControl = (SSP_DMA_SIZE & 0x0FFF)|(0x00 << 12)
|(0x00 << 15)|(0x00 << 18)|(0x00 << 21)|(1 << 26)|0x80000000;
}
else if ( DMAMode == P2M )
{
  /* Ch1 set for P2M transfer from peripheral to memory. */
  LPC_GPDMACH1->CSrcAddr = SSP1_DMA_RX_SRC;
  LPC_GPDMACH1->CDestAddr = SSP1_DMA_RX_DST;
  /* The burst size is set to 1. Terminal Count Int enable. */
  LPC_GPDMACH1->CControl = (SSP_DMA_SIZE & 0x0FFF)|(0x00 << 12)
|(0x00 << 15)|(0x00 << 18)|(0x00 << 21)|(1 << 27)|0x80000000;
}
else
{
  return ( FALSE );
}
  }
  else
  {
return ( FALSE );
  }
  return( TRUE );
}

///////////////////////////////////////////////////////////////////////////////

you see !

LPC1768 is capable for only half duplex transfer for SSP/SPI  by GPDMA !

only one mode  (P2M  for receive data from SPI(MISO) to memory) or (M2P  for sending data from memory to SPI (MOSI) ) !

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

isn't it confusing ?

SPI is a full duplex peripheral.

and it should be considered in GPDMA  design !

we need P2M2P  mode for this...

//////////////////////////////////////////////////

I am confused,

it was simply done in old AT91SAM7X256 ....

//////////////////////////////////////////////////

AT91SAM7X256: DOC6120

22. Peripheral DMA Controller (PDC)
22.1 Overview
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as
the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral
DMA Controller avoids processor intervention and removes the processor interrupt-handling
overhead. This significantly reduces the number of clock cycles required for a data transfer and,
as a result, improves the performance of the microcontroller and makes it more power efficient.

============

The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral.

=============================== THIS IS FULL DUPLEX ======================================

One channel in the pair is dedicated to the receiving channel and one to the transmitting
channel of each UART, USART, SSC and SPI.

==========================================================================================

The user interface of a PDC channel is integrated in the memory space of each peripheral. It
contains:
• A 32-bit memory pointer register
• A 16-bit transfer count register
• A 32-bit register for next memory pointer
• A 16-bit register for next transfer count
The peripheral triggers PDC transfers using transmit and receive signals. When the programmed
data

==============================================================================================

it seems that :

the GPDMA cannot handle full duplex in SSP/SPI  ( sending 1024 bytes array and receiving 1024 bytes array simultaneously )

and I have to build it without GPDMA and by byte transfer interrupts
"10 times per second each 1024 bytes" = 10240 interrupts will be over head to
my full featured heavy and complicated design,

================================================================================

any comment ?

am I wrong ?