I have a weird problem where the Timer1 match register interrupt handler is failing to be serviced when a GPDMA terminal count interrupt fires a few microseconds beforehand and the DMA IRQ handler is actively running. The Timer1 IRQ handler is being serviced normally when no other interrupts are pending or actively being serviced, the trouble only happens when the DMA handler is active. My reading of the Cortex-M3 NVIC is that:
I have confirmed the following:
Has anyone encountered a problem like this? Am I missing something obvious?