LPC1549 USB pins power consumption

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LPC1549 USB pins power consumption

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daveadshead
Contributor I

I am using an LPC1549 in an IOT application and I had some issues with power consumption.  After a week-long investigation, I found something very odd and wondered if anyone else had come across this or if NXP would like to comment...

My application doesn't use USB so I left the D+/D- pins unconnected.  I found that touching the pins dramatically changes the power consumption in power down mode.  Table 34 of the datasheet says that if the USB PHY is off, the pins are LOW.  However, applying an external pull-up actually reduces the chip power consumption.  So I concluded that the pins are not driven when the PHY is off.  Turning on the 1k5 internal pullup on D+ reduces the chip current consumption and shorting D- to D+ in this mode (so both pins are high) reduces current to <10uA.  By comparison, without these workarounds, current consumption was ~500uA at -10C, ~100uA at 25C and ~60 at +50C.  Quite the opposite to what you would normally expect i.e. leakage increasing with higher temperature.

So I have 3 questions:

1. Does NXP know about this?

2. Why does the datasheet say the pins are pulled low?

3. Has anyone else had this problem?

And finally, I am posting this to help out anyone who might be having power consumption problems.  I know it is difficult to find every last uA.

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daveadshead
Contributor I

Hi Jeremy,

     This is what I think you would need to do to reproduce the problem on the OM13056 board...

1. First this board uses USB.  You would probably need to cut the USB tracks to the CPU or, at the least, remove the protection part (U3 PRTR5V0U2X).  This is because there could be enough leakage through the part to pull D+/D- to valid logic levels.  It is also possible that voltages outside the power rails are responsible for the excess current consumption and this part would stop that from happening.  Remember, I am not using USB and I am following the datasheet recommendation to leave D+/D- unconnected.  So you need to replicate this.

2. I am using a 48-pin part but I believe the die is the same as the 64-pin part, so that shouldn't be an issue.

3. You need to go into power down mode.  My GPIOs are mixed input/output but I don't think that is relevant - just set all your outputs LOW and turn off all the GPIO pullups.  Then turn off all the clocks and peripherals and go to power down mode (I leave the RTC running).  This should reduce the current to about 5uA for the CPU.

4. However, I found this results in 30-60uA.  Touching D+/D- makes a huge different, sometimes 1mA.  However, if you pull up D+/D- to 3.3V (or presumably pull down), the current consumption drops to <10uA.

5. Since my board is already made, I used the trick in my OP where I turn on the D+ pullup and short the D+/D- pins.  On my board this results in 7uA power for the whole product (about 1uA on the 3.3V regulator, 1uA for the RTC and the rest in the LPC1549).  This aligns well with the datasheet value.

I believe what is happening is the D+/D- pins are left floating when the USB PHY is turned off.  Non-logic levels on D+/D- including the possibility of levels above and below the power rails result in excess current consumption.  Anything that pegs the pins to a reasonable level stops the excess current.

Dave

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jeremyzhou
NXP Employee
NXP Employee

Hi Dave Adshead,

Thanks for your reply.

I will give it a try.
Have a great day,
TIC

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jeremyzhou
NXP Employee
NXP Employee
Thank you for your interest in NXP Semiconductor products and 
the opportunity to serve you.
I was wondering if you can introduce the steps of testing, then I can replicate this phenomenon on LPCXpresso1549(OM13056) board.
I'm looking forward to your reply.
Have a great day,
TIC
 
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