LPC1343 I2C master wrong frequency

[lpcware]

Content originally posted in LPCWare by an.kh. on Tue Jul 16 02:06:56 MST 2013
Hello!
I have found that I2C master clock frequency is slower than it must be.
For example, for 1 MHz clock it is needed to set divider to 72 MHz / 1 MHz = 72. With this setting, the resulting frequency is around 880 kHz. And so with 400 kHz... To set 1 MHz it is needed to set divider to 65 (h=33,l=32), for 400 kHz divider = 173 (h=87,l=86).

I am using standard startup files for 72 MHz with 12 MHz crystal and SSP port showing the correct calculated frequency, so main clock is indeed 72 MHz and the problem is with I2C only. Also I didn't find any errata regarding this problem. Does anyone know the origins of this problem and what can be done with it?

[lpcware]

Content originally posted in LPCWare by Wouter on Tue Jul 16 23:48:43 MST 2013
That's right indeed.

Configuring the pins for Fast-mode Plus using IOCON and decreasing the value of your pull-up resistor may improve the rise- and fall-time

[lpcware]

Content originally posted in LPCWare by an.kh. on Tue Jul 16 06:44:54 MST 2013
Yes, I think this is it.
Main clock is ok, all other peripherals (SSP, timers, systick...) are working at requested frequencies. CLKOUT also shows 72MHz.

As I understand, high and low dividers adjusting high and low times without rise and fall times. Is this correct?

[lpcware]

Content originally posted in LPCWare by Wouter on Tue Jul 16 03:55:28 MST 2013
Most probably you're experiencing the effect of I2C clock stretching: http://www.lpcware.com/content/forum/i2c-clock-rate

To verify you're running the core/peripherals at the speed you had intended them to run on, you can indeed use the clkout pin as Serge mentioned.

[lpcware]

Content originally posted in LPCWare by serge on Tue Jul 16 03:45:00 MST 2013
You can use the CLKOUT pin and set it to different points within your clocksource and scope the signal on the clkout pin (read chapter 3 of the UM10375)
This way you can determine where it goes wrong.