I am getting strange behaviour when attempting to transmit and receive using the GPDMA for the SSP peripheral. It seems the receive FIFO is not updating the receive buffer specified in the GPDMA channel registers. I have to physically read the data register otherwise nothing is transferred to the buffer. I have counted the number of reads needed and it does not match the number of bytes in the transfer.
I am attempting to read the device ID from AT25DF321 flash device, which according to the datasheet has no dummy byte requirements.
Here are the register values at the start of the transmission:
CH0
DMACCSrcAddr 0x10000970 (Hex)
DMACCDestAddr 0x40088008 (Hex)
DMACCLLI 0x0 (Hex)
DMACCControl 0x84000004 (Hex)
DMACCConfig 0x2c801 (Hex)
CH1
DMACCSrcAddr 0x40088008 (Hex)
DMACCDestAddr 0x10000970 (Hex)
DMACCLLI 0x0 (Hex)
DMACCControl 0x88000004 (Hex)
DMACCConfig 0xd003 (Hex)
DMACIntStat 0x0 (Hex)
DMACIntTCStat 0x0 (Hex)
DMACIntTCClear 0x0 (Hex)
DMACIntErrStat 0x0 (Hex)
DMACIntErrClr 0x0 (Hex)
DMACRawIntTCStat 0x0 (Hex)
DMACRawIntErrStat 0x0 (Hex)
DMACEnbldChns 0x3 (Hex)
DMACSoftBReq 0x500 (Hex)
DMACSoftSReq 0x0 (Hex)
DMACSoftLBReq 0x0 (Hex)
DMACSoftLSReq 0x0 (Hex)
DMACConfig 0x1 (Hex)
DMACSync 0x0 (Hex)
SSP0
CR0 0xff07 (Hex)
CR1 0x2 (Hex)
DR 0x0 (Hex)
SR 0x3 (Hex)
CPSR 0x2 (Hex)
IMSC 0x0 (Hex)
RIS 0x8 (Hex)
MIS 0x0 (Hex)
ICR 0x0 (Hex)
DMACR 0x3 (Hex)
I am not performing any actions when channel 0 has completed its transfer, just clearing the GPDMA interrupt flags.
During the channel 1 transfer complete interrupt:
uint32_t count = 0;
/* Ensure that transfer has completed. */
while (0 != (reg_struct->SR & ((1 << 4) | (1 << 2)))) << freezes here until data register is read
{
volatile uint8_t temp = reg_struct->DR;
++count;
}
count = 15
The values in the receive buffer are valid despite having to do 15 DR reads.
In other transfers the count can be up to 180. Again the commands used have no dummy byte requirements.
Does anyone know why this could be happening?
