Hi Carlos,
Thank you for your interest in my issue.
The sequence I shared with you is the issue. I didn't expect any thing like this. I just initialized my LCD controller than I use it normally. This sequence appear when I restart debug. So each time I'm obliged to stop debug, reset my board than run debug again. I'm asking my self, where this shown sequence is stored?. Is it a sequence that the LPC1788 display when some issue occurs on the LCD Controller? I heaved searched everywhere an issue like this but without any result. So thank you again for helping me
About my source code, I start developing using the LPCOpen, the one you found with LPCXpresso. I have adopted the same software architecture of the EA1788 board because I like it. Of course I have modify the part like SDRAM & LCD in board.h&c.
const LCD_CONFIG_T RK043FN07H = { /* Rocktech Displays Limited */
28, /* Horizontal back porch in clocks */
10, /* Horizontal front porch in clocks */
2, /* HSYNC pulse width in clocks */
LCD_HEIGHT, /* Pixels per line */
2, /* Vertical back porch in clocks */
1, /* Vertical front porch in clocks */
2, /* VSYNC pulse width in clocks */
LCD_WIDTH, /* Lines per panel */
0, /* Invert output enable, 1 = invert */
0, /* Invert panel clock, 1 = invert */
0, /* Invert HSYNC, 1 = invert */
1, /* Invert VSYNC, 1 = invert */
1, /* AC bias frequency in clocks (not used) */
5, /* Maximum bits per pixel the display supports */
LCD_TFT, /* LCD panel type */
LCD_COLOR_FORMAT_BGR, /* BGR or RGB */
0 /* Dual panel, 1 = dual panel display */
};STATIC const IP_EMC_DYN_CONFIG_T IS42S16160D_config = {
EMC_NANOSECOND(64000000 / 4096),
0x01, /* Command Delayed */
3, /* tRP */
7, /* tRAS */
EMC_NANOSECOND(70), /* tSREX */
EMC_CLOCK(0x01), /* tAPR */
EMC_CLOCK(0x05), /* tDAL */
EMC_NANOSECOND(12), /* tWR */
EMC_NANOSECOND(60), /* tRC */
EMC_NANOSECOND(60), /* tRFC */
EMC_NANOSECOND(70), /* tXSR */
EMC_NANOSECOND(12), /* tRRD */
EMC_CLOCK(0x02), /* tMRD */
{
{
/* Base address */
EMC_ADDRESS_DYCS0,
/* RAS */
3,
/* Mode Register value */
EMC_DYN_MODE_WBMODE_PROGRAMMED |
EMC_DYN_MODE_OPMODE_STANDARD |
EMC_DYN_MODE_CAS_3 |
EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
EMC_DYN_MODE_BURST_LEN_4,
/* Dynamic Configuration value */
EMC_DYN_CONFIG_DATA_BUS_16 |
EMC_DYN_CONFIG_SDRAM |
EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS |
EMC_DYN_CONFIG_MD_SDRAM
},
{0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0}
}
};Best regards
