Content originally posted in LPCWare by tjoAG on Mon Jun 11 02:19:27 MST 2012
Hi Kevin
I'm not 100% sure I program the MODE correctly, but I think so.
I'm using MICRON MT48LC8M16A2 128 Mbit SDRAM, R=12, C=9, Banks=4
Row addressing is A0-A11
Collumn addressing is A0-A8
Bank selection is BA0-Ba1
I'm running the EMC clock at 120 MHz, so according to the datasheet a CAS latency of 3 must be used.
RBC mode:
I set the Dynamic Config mode to 0x480 (RBC mode) and the use mode word is
<code>wtemp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x33<<(12)))); /* 8 burst, 3 CAS latency */ </code>
I then use this code, just to verify the SDRAM:
<code>
// 16 bit write
for (i=0; i<(0x01000000/2); i++)
{
*short_wr_ptr++ = 0xAAAA;
}
/ 16 bit read
short_wr_ptr = (uint16_t *)0xA0000000;
for (i=0; i<(0x01000000/2); i++)
{
if(*short_wr_ptr != 0xAAAA)
{
while(1);
}
short_wr_ptr++;
}
</code>
When I use the above SDRAM init code (RBC), the RAM validation work.
I know it is not a in depth RAM test, but if that doesn't work something is wrong.
BRC:
In BRC mode I'm doing this instead:
I set the Dynamic Config mode to 0x1480 (BRC mode) and the use mode word is
<code>wtemp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x33<<(10)))); /* 8 burst, 3 CAS latency */ </code>
Then I have memory holes at:
0xA040 0000 - 0xA071 ffff
0xA0C0 0000 - 0xA100 0000
The other location seems to work.
When I run in the RBC mode, the data in SDRAM keeps changing when the LCD gets enabled
When I run in the BRC mode, the data is SDRAM dont keep changing when the LCD gets enabled. Data is shown fine on the display, but I have memory hole where I can write read?!!!
The MODE word can still be wrong?
What about the MD (LP SDRAM) setting?
Do I read the SDRAM datasheet wrong?
Is the SDRAM connected wrong to the CPU. Maybe I set the wrong collumn, bank, burts length in the MODE word?
Please see below for the used pins and complete init code.
/Thomas
CPU pin | SDRAM
-----------------
A0 <--------> A0
A1 <--------> A1
A2 <--------> A2
A3 <--------> A3
A4 <--------> A4
A5 <--------> A5
A6 <--------> A6
A7 <--------> A7
A8 <--------> A8
A9 <--------> A9
A10 <-------> A10
A11 <-------> A10
A12 <-------> BA0
A13 <------> BA1
<code>
uint32_t i, dwtemp;
TIM_TIMERCFG_Type TIM_ConfigStruct;
/* Initialize EMC */
InitSDRAMPins();
TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
TIM_ConfigStruct.PrescaleValue= 1;
// Set configuration for Tim_config and Tim_MatchConfig
TIM_Init(LPC_TIM0, TIM_TIMER_MODE,&TIM_ConfigStruct);
//Configure memory layout, but MUST DISABLE BUFFERs during configuration
LPC_EMC->DynamicConfig0 = 0x00000480; /* 128B, 8Mx16, row=12, 4 banks, column=9 */
// Configure timing for Micron SDRAM MT48LC8M16A2-75 */
// Timing for 120MHz Bus: 8.333333 ns/clk
LPC_EMC->DynamicRasCas0 = 0x00000303; // 3 RAS, 3 CAS latency to run more then 100 MHz bus
LPC_EMC->DynamicReadConfig = 0x00000001; // Command delayed strategy, using EMCCLKDELAY
LPC_EMC->DynamicRP = 0x00000002; // Min 20ns. (n + 1) -> 3 clock cycles
LPC_EMC->DynamicRAS = 0x00000005; // Min 44 ns.(n + 1) -> 6 clock cycles
LPC_EMC->DynamicSREX = 0x00000009; // Min 75 ns. ( n + 1 ) -> 10 clock cycles
LPC_EMC->DynamicAPR = 0x00000002; // ??? ( n + 1 ) -> 2 clock cycles 5
LPC_EMC->DynamicDAL = 0x00000004; // tWR + tRP: min 35 ns (n + 1) -> 5 clock cycles
LPC_EMC->DynamicWR = 0x00000001; // Min 15 ns. ( n + 1 ) -> 2 clock cycles
LPC_EMC->DynamicRC = 0x00000007; // Min 66 ns. ( n + 1 ) -> 8 clock cycles
LPC_EMC->DynamicRFC = 0x00000007; // Min 66 ns. ( n + 1 ) -> 8 clock cycles
LPC_EMC->DynamicXSR = 0x00000009; // Min 75 ns. ( n + 1 ) -> 10 clock cycles
LPC_EMC->DynamicRRD = 0x00000001; // Min 15 ns. ( n + 1 ) -> 2 clock cycles
LPC_EMC->DynamicMRD = 0x00000001; // 2 tCK. ( n + 1 ) -> 2 clock cycles
TIM_Waitms(100); /* wait 100ms */
LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
TIM_Waitms(200); /* wait 200ms */
LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
LPC_EMC->DynamicRefresh = 0x000007ff; /* ( n * 16 ) -> 32 clock cycles */
for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
//Timing for 120MHz Bus
LPC_EMC->DynamicRefresh = 0x1d; // ( n * 16 ) -> 1872 clock cycles -> 15.60uS at 120MHz <= 15.625uS ( 64ms / 4096 row )
LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
//Timing for 48/60/72MHZ Bus
dwtemp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x33<<(12)))); /* 8 burst, 3 CAS latency */
LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */
//[re]enable buffers
LPC_EMC->DynamicConfig0
</code>