Content originally posted in LPCWare by tecow on Sun Feb 14 13:37:52 MST 2016 Hi, I am using a hardware with the LPC4370 + a 4MByte external SPI flash.
Without any obvious reason the JTAG connection stoppded working after month of proper operation (now I am using lpcxpresso 8.0) Sometimes things happen with EMC noise etc. and so I took a 2nd board and again after a week of proper operation, JTAG is again dead - this make me believe it is not EMC.
I measure the JTAG signals after initiating a flash sequence (IspReset) and saw the following strange signals:
Pin 2 (SWDIO) starts with 2.8V and went after starting the transfer to 1.5V ???? (Is the processor driving SWDIO after Reset?) Pin 4 (TCK) 10 kHz clock on TCK (Pin 4) Pin 6 (TDO) stays at 3.3V Pin 7 (a nice low pulse for 5ms) after switched to lpcxpresso 8.
I don't think it is a issue with my JTAG configuration. It works with another board and also with the LPC-Link as Debug Target. I am just wondering if I really damaged 2 boards or is there any possiblity how the JTAG interface can be brought statically into such a state (CRP prog, by chance?) Do you see any way to re-enable JTAG?
Content originally posted in LPCWare by lpcxpresso-support on Wed Feb 17 11:05:41 MST 2016
You didn't mention if this is custom or NXP hardware.
A couple of questions:
1. Is your application using any of the CRP settings? 2. Does your application on purpose, or by accident redirect any pins used for debug signals?
If you can't recover your board by booting into the ISP, you might still be able to erase your part using FlashMagic. Any CRP setting of 1 or above disables debug. If you've done either of the above, once you've erased flash you should be able to recover provided the offending code is disabled/removed.
After erasing flash, if you find JTAG/SWD debug is still not viable, then your debug circuit is probably damaged. Such damage is often static related, although it's sometimes possible to damage the debug circuit by mis-socketing the debug ribbon cable.
Content originally posted in LPCWare by tecow on Tue Feb 16 15:38:32 MST 2016 Yes of course, that helps nicely when the PLL is blocked etc. But if the ISP mode is entered correctly, the M4 should enter a stable state and the JTAG should be accessible. My question was, is there any way how the JTAG can be disabled by accident?