Issues about SSP in SPI Mode (Chip Select Pin)

[lpcware]

Content originally posted in LPCWare by Witte on Thu Sep 25 12:44:30 MST 2014
Hey there,

I'm using SSP1 in SPI Mode on my project and I have a problem with the CS Pin.
I notice what each byte sent the CS Pin is put in High. For me this is a problem, because I need the pin in LOW until the last byte of my package.

Looking for a resolution in the forum I found this link: http://www.lpcware.com/content/forum/ssp-port-problem-spi-mode

This guy have the same problem... The question is... This BIG BUG on SSP peripherical occurs on LPC43xx Family too?

I resolve the problem configuring the CS Pin with a simple GPIO. So, I set the state manualy.

Thanks!

[lpcware]

Content originally posted in LPCWare by JohnR on Fri Oct 03 05:50:21 MST 2014
Hi Witte,

I do the same as you - use a separate I/O and keep it low for the whole transmission.

I use the same pin for SSP1_SSEL (P1_20) but declare it as GPIO0[15], mode0.

JohnR

[lpcware]

Content originally posted in LPCWare by Witte on Wed Oct 01 11:40:36 MST 2014
anybody?

NXP Team?