Is the GPIO status maintained if I remove the peripheral feed?

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Is the GPIO status maintained if I remove the peripheral feed?

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asiertapiazulai
Contributor III

I am following the guidelines of AN10915 to reduce the energy consumption of an LPC1769. I run WFI in the infinite loop, I have disabled the peripherals, I have enabled the flash accelerator, I have disabled the BOD, I have connected the USB PLL and I have configured the pins that I do not use as low level outputs.

To do the latter I have fed the GPIO. My question is, can I disable it again? That is, if I then disable the GPIO, will the pins continue to be configured as outputs at a low level? Or should I leave the GPIO fed?

Thank you.

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asiertapiazulai
Contributor III

Hi XiangJun,

Indeed, the pins maintain their state. I have configured most of the pins as outputs at a low level (I have left some at a high level to compare) and I have used an LED that turns on at a low level (with the anode at 3.3 V and the cathode to the pin). And I checked the state of the pins at three points:
1) After configuring them as low level outputs, to check.
2) After gated off the GPIO.
3) Once the processor enters sleep mode.

And in all three points the pins have kept the level low (the LED has lit). So we must conclude that the pins maintain their status despite gated off the GPIO, right?

Thank you so much for your help, XiangJun.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Asier,

Yes, you are right, the pins maintain their status despite gated off the GPIO. But if you write/read GPIO register, the GPIO gated clock must be enabled.

BR

XiangJun Rong

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asiertapiazulai
Contributor III

Thank you very much, XiangJun Rong.

That was not exactly the question, but you answered it indirectly. In AN10915 it is recommended to configure the pins that are not going to be used as low-level outputs: "All General Purpose I / O pins (GPIO) default to input with pull-up resistor enabled. Using the PINMODEx registers, first, disable the internal pull-ups on all general port pins. Second, configure the IOs as GPIO outputs and drive them low " (p. 13).

It is also recommended to remove power to peripherals that are not to be used: "Peripherals Power Control Register contains control bits that enable and disable individual peripheral functions, allowing elimination of power consumption by peripherals that are not needed. This feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings" (p. 12).

I am trying to create a generic function to apply all the recommendations of AN10915. The idea would be to execute this function at the beginning of my projects, then configure the hardware according to the needs of said project (by feeding the necessary peripherals) and, finally, in the infinite loop, put the processor in sleep mode (since It is the only one that supports debug mode).

Therefore, within this function for energy saving, my intention was, once the pull-ups have been deactivated and the pins configured as outputs at a low level, turn off all peripherals:
LPC_SYSCTL-> PCONP = 0x0;
And then, in the main function, feed the peripherals to be used in each project.

From your answer I deduce that if I remove the power supply from the GPIO, the state of the pins is not maintained. So I should first turn off the peripherals, then power the GPIO, configure the pins that I will not use, and leave the GPIO powered. It is right?

Sorry for the level of English (I'm using a translator). Thank you very much for your help.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Asier,

I see you procedure, firstly, you configure the PCGPIO bit in PCONP reg to enable the GPIO clock, then you configure the GPIO in output mode and output LOW logic. Then you disable the GPIO clock  by clearing the PCGPIO bit in PCONP reg(GPIO clock is gated off), then have the chip enter to deep-sleep mode. After the sleeping mode, I think the GPIO pin will keep to LOW even if the GPIO clock is gated off. But I have not the board on hand, I never have a try, you have to do a test yourself.

BR

XiangJun Rong

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Asier,

Frankly speaking, I do not know your question clearly. For GPIO mode for example, the GPIO pin is configure as GPIO output mode and the pin outputs HIGH logic in normal mode, do you ask if the GPIO pin can keep it's high logic in low power mode?

As you know the LPC processor has four low power modes:sleep, deep-sleep, power-down and deep-power-down modes, when you enters low power mode from normal mode, in sleep/deep-sleep modes, the GPIO pin can remains it's state., for example the GPIO pin can keep it's state, for example, if it is high logic before the low power mode, it keeps the high logic.

After entering low power mode, if the low power mode is power-down or deep-power-mode, the GPIO can NOT keep it's original state, in the case, after waking-up, you have to reinitialize the GPIO register.

If it is not what you expected, I am sorry,pls clarify your question.

BR

XiangJun Rong