Implement mutex / semaphore on LPC1227

[lpcware]

Content originally posted in LPCWare by jackiechau on Wed Oct 30 20:24:42 MST 2013
I found that mutex is provided by RTX OS. But I would like to know how to implement mutex/semaphore on LPC1227 without OS, please kindly advise.

[lpcware]

Content originally posted in LPCWare by MarcVonWindscooting on Fri Nov 01 06:29:07 MST 2013
There are no instructions supporting semaphores in the M0 prozessor.
No SWP, no LDREX, no bit-banding.
That's funny, escpially if there are devices like LPC4300 (dual core, M0 + M4). The synchronization between the two cores is done by a special hardware. I guess because semaphore synchronization would make it harder to do power saving/sleeping.

Disabling interrupts is a questionable operation on a M0, because that defeats the priorities of interrupts and NVIC's possibility to nest interrupts: low priority ISR does disable interrupts => higher priority interrupts stalled. Yes I know, these should be disabled only for short times. Nevertheless, disabling interrupts increases interrupt latency (and jitter).
Even the 8051 had a bit test-and-set (or similar, I don't remember any more). Why is that so expensive to implement on a M0??

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Wed Oct 30 22:12:39 MST 2013
If you don't have an RTOS, what do you need a mutex for? Without an RTOS, the only thing that could cause a problem is an interrupt - and you can just disable interrupts during your critical code.