I2S interface State Register

[lpcware]

Content originally posted in LPCWare by jdowd on Mon Jul 21 11:16:15 MST 2014
On reset the state register of the I2S module are set. The user manual states that the bit reflects the presence of an interrupt for either the Rx/Tx side or there is a bit each for DMA1 or DMA2 interrupts pending.

Can anyone verify that these bits are actually working? I've run the demo s/w for the I2S and those bits never change. There does not appear to be a way of clearing them.

My own code gets interrupts on the Tx portion of the i/f but those bits still never change no matter what actual state the i/f is in.

I really need some clarification on this interface.

I'm running in slave mode as well. I'm not sure how that can affect these "state" bits but there it is.

Cheers!!

[lpcware]

Content originally posted in LPCWare by jdowd on Mon Aug 18 06:48:18 MST 2014
I now have a working "slave" mode I2S interface. Yes, the state register does show correctly. I'm having great difficulty with the NXP User Manual. The information does not seem complete to me. I'm more used to ST-M and ATMEL datasheets and User Manuals. They are by no means perfect but I find their format a bit easier to interpret.

Cheers!!

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Fri Aug 15 16:47:13 MST 2014
Hi, jdowd,

Did you resolve the issue?

I double checked with the LPCOpen sample code with the EA development board, the STATE register seems to be well and alive.

regards.