I2S in RX master mode with external MCLK (urgent)

[lpcware]

Content originally posted in LPCWare by dcorrigan on Mon Sep 28 10:27:33 MST 2015
Has anyone used the LPC1820 I2S driver in RX master mode with an external MCLK? (Figure 147 in User Guide)

I want to run the I2S0 port in master mode, providing the WS an BCLK signals, with BCLK at 3MHz and WS at 46.88 kHz, two allow for stereo, 32 bits.
As the application is sensitive to jitter, I will be providing an external clock through the MCLK pin.

So far I am supplying an external 3MHz clock to MCLK, and after a lot of work, I have managed to generate a WS clock at 46.8kHz. However, there is nothing coming out of my SCK pin at all.
I thought that maybe MCLK is meant to be oversampled, so I tried bumping it up to 27MHz (straight from xtal), and still I can get only a WS signal.

I have the part configured as:
DAI:
Wordwidth = 32 bits
Mono = 0
Stop = 0
Reset = 0
WS_SEL = 0
WS_HALF = 0x1F

RXRATE = 0
RXBITRATE = 0x08 (for 27MHZ MCLK), or 0x0 (for 3MHz MCLK).

RXMODE:
CLKSEL = 0x01
RX4PIN = 0
RXMCENA = 0


I have previously had this system working using an internally generated clock, but I really need to use the external mclk to get the jitter performance I need.



An interesting note:
The I2S bus seems to be "listening" okay, when I wire my MCLK straight to the SCK line, and I get data from the source, I can see it beign buffered up and read back to the pc, and it looks like good data. It seems like my issue lies somewhere between receiving MCLK and the LPC1820 generating the SCK signal.

Any help is greatly appreciated as I'm very short on time to get this fixed!!

Thanks,
D

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Oct 06 03:52:36 MST 2015
No way that you can use the on-chip AudioPLL for generating the required clock?
Or did you already use it?

Regards,
NXP Support Team.

[lpcware]

Content originally posted in LPCWare by dcorrigan on Mon Sep 28 10:56:49 MST 2015
Just to clarify,

With either a 3MHz or 27MHz external MCLK, I am able to generate the appropriate 46.88kHz WS signal, but there is nothing coming out on my SCK line.

The RXFIFO is filling, and my DMA requests are being handled appropriately. So the I2S driver is reading in data.

My problem is that there is no SCK being generated/output on the SCK pin.

When I set my MCLK signal to 27MHz, I set my RX bit rate to X = 2, Y = 9. This should generate a 3MHz signal from the 27MHz, although from the diagram, it looks like this fractional divider is not applied to an external MCLK supply (this is why I was originally trying to drive MCLK with 3MHz).

Finally, using the same pin configuration I was able to have a fully functioning bus using the internal clock (but jitter was too high).

Thanks,
D