Help me choose: SSP or SGPIO

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Help me choose: SSP or SGPIO

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NXP Employee
NXP Employee
Content originally posted in LPCWare by mark03 on Mon Oct 22 17:54:28 MST 2012
I'm interfacing a serial A/D (LTC237x series) to an LPC4357, and trying to decide the optimal solution for having the data transfer "in the background" as much as possible.  Ideally I would like the data to fill a DMA buffer in RAM without spending any CPU cycles until the buffer needs emptying.

I will drive the A/D conversion clock with a GPIO timer/counter output.  The A/D indicates it is done by the falling edge of a BUSY signal, and requires the host to provide SCLK and read the bits back.  Based on my reading of the LPC user's guide, if I use SSP the only way I can perform a read is to write dummy words.  The SSP has a nice FIFO, which would probably suffice in place of a DMA buffer, IF I could have that FIFO filling autonomously, but it's not clear to me that this is possible.  I can't just load up the transmit FIFO, then sit back and wait, because the SSP must only transmit/receive a frame when an A/D sample is ready.  I don't see any way to achieve this without CPU involvement (interrupt based).

Not really liking that prospect, I was looking at SGPIO.  There's no sample FIFO there (only the bit FIFOs for deserialization), so I would want to use DMA.  The user's guide says this is possible, but has anyone actually tried it [successfully]?  I'd feel a lot better with a working example to look at.

Any other suggestions?

Thanks,

Mark
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NXP Employee
NXP Employee
Content originally posted in LPCWare by mark03 on Tue Oct 23 10:14:07 MST 2012
Looking at the LT datasheet, I believe the conversion-start input can be a square wave (50% duty cycle).  Either way, it should be easy to make with a plain-old timer0/1/2/3 match output, assuming your application needs periodic sampling.

Another wrinkle is that to do this right, you should only have 16 SCLK cycles; active SCLK outside this time wastes power.

Is the SGPIO capable of being triggered somehow, in a one-shot fashion, by the falling edge of an input pin?  I need it to wait for the falling edge of BUSY, then zap out the 16 SCLKs while reading in the bits, then wait again for the next BUSY de-assertion.
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NXP Employee
NXP Employee
Content originally posted in LPCWare by JohnR on Tue Oct 23 05:45:21 MST 2012
Hi,

I dno't think you can easily use the SSP. The convert pulse for the Linear converters is non-standard - they require a short pulse that starts the conversion rather than the normal chip select.

NXP's AN11210 contains a description and example of the use of the SGPIO. I modified it to interface to a LTC1407A which reads out two sets of 14-bit data sequentially. I had to supply the conversion pulse from a separate GPIO output. I am still working on a version to read a single 14-bit conversion (LTC2355).

The SGPIO block is extremely flexible but complicated, at least to me, and the one NXP publication does not really give enough details of its usage. Also I found it difficult to relate some of the circuit blocks in the diagrams given in the UM10503 manual to the various configuration registers.

John.







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