HSADC problem with variable offset of sampled signals

[lpcware]

Content originally posted in LPCWare by ukovac on Tue Apr 26 02:55:24 MST 2016
Hello,

I would like to use HSADC with DMA to continuously sample four signals on separate channels of AD. I use 4 descriptors to change channels. The DMA is used to copy data from FIFO_OUTPUT register to circular buffer. The address of the copy destination is set after each copy in DMA Handler. I know this is not ideal and I will use LLI approach in the future but I don't think this is the source of my problems as we are currently testing the AD and we're using rather low sampling frequency at around 1MHz.

My main problem is that after two separate starts of HSADC the offsets of the sampled signals is not always the same. An example of sampled signals after two separate starts of AD is presented in the attached figure 1.

For testing purpose we have all the HSADC pins shorted (attached figure 2), so we acctually measure 0V which should produce around 2048 in binary offset mode.

[img=507x308]http://shrani.si/f/3K/7n/1yGEhIji/fig1.png[/img]
Figure 1

[img]http://shrani.si/f/3V/zZ/3a3b4ggP/fig2.png[/img]
Figure 2

HSADC start code.
After start of HSADC and DMA we manually trigger the end of sampling, stop the sampling and collect the sampled signal.

LPC_ADCHS->POWER_DOWN = 0;
LPC_ADCHS->FLUSH = 1;
    
match = 3 - 1;
//ADCHS_CLK - 0x06...12MHz XTAL
BASE_ADCHS_CLK = (1 << 11) | (0x06 << 24);
LPC_CCU1->CLK_M4_ADCHS_CFG = 1;

//fifo config
Chip_HSADC_SetupFIFO(LPC_ADCHS, DATA_COUNT_IN_WORDS, true);
        
/* Select both positive and negative DC biasing for input 3 */
Chip_HSADC_SetACDCBias(LPC_ADCHS, 2, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_NODCBIAS);
Chip_HSADC_SetACDCBias(LPC_ADCHS, 3, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_NODCBIAS);
Chip_HSADC_SetACDCBias(LPC_ADCHS, 4, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_NODCBIAS);
Chip_HSADC_SetACDCBias(LPC_ADCHS, 5, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_NODCBIAS);

//binary offset
LPC_ADCHS->POWER_CONTROL |= 0 << 16;
    
//trigger config
Chip_HSADC_ConfigureTrigger(LPC_ADCHS, HSADC_CONFIG_TRIGGER_SW, HSADC_CONFIG_TRIGGER_RISEEXT, HSADC_CONFIG_TRIGGER_NOEXTSYNC, HSADC_CHANNEL_ID_EN_ADD, 0x90);
    
//adc speed
LPC_ADCHS->POWER_CONTROL |= 0;
LPC_ADCHS->ADC_SPPED |= 0xFFFFFF;
    
//set descriptors
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 0, (HSADC_DESC_CH(4) | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(match) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 1, (HSADC_DESC_CH(2) | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(match) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 2, (HSADC_DESC_CH(3) | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(match) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 3, (HSADC_DESC_CH(5) | HSADC_DESC_BRANCH_FIRST | HSADC_DESC_MATCH(match) | HSADC_DESC_RESET_TIMER | HSADC_DESC_UPDATE_TABLE));
                                                
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 0);
Chip_HSADC_SetActiveDescriptor(LPC_ADCHS, 0, 0);

dmaSetup();

Chip_HSADC_EnablePower(LPC_ADCHS);
Chip_HSADC_EnableInts(LPC_ADCHS, 0, HSADC_INT0_FIFO_OVERFLOW);

LPC_ADCHS->CLR_STAT0 = 0x7f;    
LPC_ADCHS->CLR_STAT1 = 0x7f;

/* Enable HSADC interrupts in NVIC */
NVIC_ClearPendingIRQ(ADCHS_IRQn);    
NVIC_SetPriority(ADCHS_IRQn, 1);
NVIC_EnableIRQ(ADCHS_IRQn);

Chip_HSADC_SWTrigger(LPC_ADCHS);

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