GPIO interrupt registers

[lpcware]

Content originally posted in LPCWare by Divya on Tue Oct 22 22:29:27 MST 2013
In LPC43XX, among GPIO interrupt registers there are three registers.
1.ENAF (Pin interrupt active level (falling edge) interrupt enable register)
2.SETENAF (Pin interrupt active level (falling edge interrupt) set register)
3.CENAF (Pin interrupt active level (falling edge interrupt) clear register)

I am unable to differentiate between the operation of ENAF and SETENAF when both are 1.
And also when ENAF is 0 and CENAF is 1.
And I am also unclear about the exact functionality of the above registers.

If anyone could explain me with an example it would be helpful.
Thanks in advance.

[lpcware]

Content originally posted in LPCWare by starblue on Thu Oct 24 04:54:00 MST 2013
Writing to SETENAF or CLENAF is a single atomic operation.

If you had only ENAF you would need to read the value, modify it and write the modified value.
If an interrupt happens in the middle and also modifies it that modification would be overwritten.
This can cause very nasty and hard to find bugs that only happen sporadically.

[lpcware]

Content originally posted in LPCWare by Divya on Thu Oct 24 03:47:34 MST 2013
Yes, on setting or clearing those values we are issuing commend.
But I am not getting what is the use of 3 different registers for issuing the same type of command?

Please correct me if my question is wrong...
Thank you.

[lpcware]

Content originally posted in LPCWare by starblue on Thu Oct 24 02:40:13 MST 2013
You need to think of writing to SETENAF and CENAF as issuing a command, not as writing data.

The command is to set or clear certain bits in ENAF, respectively (and leaving the other bits unchanged).