Content originally posted in LPCWare by milind.mishra on Mon Feb 16 01:41:31 MST 2015
Hi,
I am using the I2S DMA driver, provided by NXP, with ucOS-iii.
Whenever a request to start recording is received from the host, following steps are taken:
1) Buffer is allocated to store the data from the I2S.
2) The Buffer pointer and the Transfer size is set passed to the 'pDMAch' structure.
After setting up the DMA, I enable the corresponding channel dedicated for the I2S..
I, however, observe that the transfer size field in the register always remains zero thereby indicating the DMA controller that the DMA transfer is done, hence I tend to get very frequent interrupts.
So, is there a particular order in which I should configure the controller or is it indicative of a hardware problem?
Code:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign memory destination address
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl = GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
pDMAch->CControl |= GPDMA_DMACCxControl_TransferSize(((uint32_t)GPDMAChannelConfig->TransferSize)/4);----> is Always Zero
Regards,
Milind.
