Ethernet receiving issue in LPC54608

[TEMCEFF]

hi,

      iam facing problem in receiving the data in ethernet in LPC 54608 ,plze help me

these are the following observations

 1.iam using the standard drives from the SDK_2.3.0_LPC54608J512 file , i changed the pin config according to the my deigned board.

my pin configuration is RXD0 -P0_13,   

RXD1 -          P0_14,

TXD0 -            P4_8,

TXD1 -          P0_17,

MDIO-           P4_16,

MDC-            P5_3,

REF_CLK    P4_14,

TX_EN         P4_27,

CRS_DV      P2_2,

when loop back internally  using MAC_CONFIG LM bit the data is receiving.

2.iam using LAN8720 phyter IC in application when we configured near end loop back in LAN8720 the signal is appearing on RXD0,RXD1 pins  correctly but no data receiving in the buffers.

3. the data is transmitting data correctly we verified in wireshark

[Dezheng_Tang]

Other than the IO pin configuration, I suspect it may be related to the REFCLK_O signal from the PHY which has some propagation delay, I hope that you have used the schematics below as the reference for your board design:

https://www.nxp.com/support/developer-resources/hardware-development-tools/lpcxpresso-boards/lpcxpre...

and make sure the circuitry near the crystal and REFCLK_O is correct. Use the LPC546xxXpresso board as the reference, if possible, monitor and compare the signals related to these signals first. 

In the past, we saw some issue with LAN8720 connecting with LPC407x board that we had to add an logic inverter

to deal with the propagation delay to make it work. However, the same MCU didn't have any problem with the DP83848 PHY. We didn't see this issue on LPC546xx EMAC though since it uses a different MAC. 

To eliminate the propagation delay completely, the safest is that you don't use REFCLK_O from the PHY and use 50MHz to connect to PHY and MAC ENET_RX_CLK signal directly. I never saw any problem with this configuration.

[TEMCEFF]

hi Tang,

 thank you for reply

i tried as you said external crystal oscillator 50MHz comman for both PHY and ENET_RX_CLK but problem is not sloved.

whether i need to verify any other things,please help me.

[Dezheng_Tang]

On the MAC side, ENET_CRS and ENET_RX_DV are two different pins. You should use ENET_RX_DV to check data valid or not,  p2.2 is ENET_CRS. Can you double check the reference design I attached earlier?