Ethernet clock source

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Ethernet clock source

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by leojose on Wed May 15 00:28:27 MST 2013
<p class="MsoNormal" style="margin: 0in 0in 0pt;"><span style="color: #1f497d;"><span style="font-size: small;"><span style="font-family: Calibri;">In LPC4076(and other relevant NXP MCUs), which clock drives the Ethernet module? Is it the <strong>cclk</strong>?</span></span></span>
<p class="MsoNormal" style="margin: 0in 0in 0pt;"><span style="color: #1f497d;"></span><span style="font-family: 'Calibri','sans-serif'; color: #1f497d; font-size: 11pt; mso-fareast-font-family: Calibri; mso-fareast-theme-font: minor-latin; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;">What is the minimum value of cclk required to drive the Ethernet module?</span>
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by leojose on Wed May 15 21:57:12 MST 2013

In that case, is there a minimum cclk freq at which the Ethernet module will operate correctly? Or can we simply say - lower is the cclk lesser is the MCU response time?

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by wellsk on Wed May 15 11:58:00 MST 2013

For the LPC407x only...


For general clocking when enabling the ethernet clock via the System and Clock Control block, it's CCLK. MDIO data transfer is via the ethernet RX_CLK/TX_CLK pin clocking (usually 25MHz (MII) or 50MHz (RMII). Internal data transfers (DMA descriptors and buffers) are on the internal AHB bus at CCLK rate.

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