Hi, I am using LPC 54018,OM 40003 in MCUXpresso IDE, I am getting the following error after debugging. This issue is happening after i tried placing variable in external SDRAM using __DATA(RAM4) command. please help me to resolve issue. I am getting same error for all the programs (simple ex like Hello world also not working). I am stuck here and not able to do anything .
ERROR :
MCUXpresso IDE RedlinkMulti Driver v11.0 (May 22 2019 13:46:40 - crt_emu_cm_redlink build 6)
Found chip XML file in C:/nxp/MCUXpressoIDE_11.0.0_2516/ide/workspace_with _rtos/LPC54018_Project_ex/Debug\LPC54018.xml
Reconnected to existing LinkServer process.
Using memory from core 0 after searching for a good core
On debug connection - use system reset, stalling when 0x40000040 is accessed
Retask read watchpoint 1 at 0x40000040 for boot ROM stall
Warning - processor did not halt - gave up waiting
Cannot halt processor
Request debug reset of DAP
Cannot halt processor
Request debug reset of DAP
debug interface type = Cortex-M3/4 (DAP DP ID 2BA01477) over SWD TAP 0
processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0
number of h/w breakpoints = 6
number of flash patches = 2
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled.
Content of CoreSight Debug ROM(s):
RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1)
ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0)
ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0)
ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0)
ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU
ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core
Cannot halt processor
Failed on chip setup: Ep(04). Cannot halt processor.
Hi Manasa,
Have you well initialized external SDRAM before you place the variable into it?
If yes, please refer below link of how to place data to different RAM
Placing data into different RAM blocks
Have a great day,
Jun Zhang
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